From nobody Fri Nov 7 13:05:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547745521521788.5137856710759; Thu, 17 Jan 2019 09:18:41 -0800 (PST) Received: from localhost ([127.0.0.1]:48507 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkBJQ-0004MI-Dn for importer@patchew.org; Thu, 17 Jan 2019 12:18:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkBGV-0002fx-Pv for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:15:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkBGT-0008MR-Ov for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:15:39 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:53272 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gkBGT-00083D-Hj for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:15:37 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x0HHEqUB094315 for ; Thu, 17 Jan 2019 12:15:27 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q2ub7fcrx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 17 Jan 2019 12:15:26 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 17 Jan 2019 17:15:08 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0HHF7WC3998064 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Jan 2019 17:15:07 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8039DA4040; Thu, 17 Jan 2019 17:15:07 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 613BEA405B; Thu, 17 Jan 2019 17:15:07 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 17 Jan 2019 17:15:07 +0000 (GMT) Received: from bahia.lan (sig-9-145-42-56.uk.ibm.com [9.145.42.56]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 26977220129; Thu, 17 Jan 2019 18:15:06 +0100 (CET) From: Greg Kurz To: David Gibson Date: Thu, 17 Jan 2019 18:15:05 +0100 In-Reply-To: <154774526588.1208625.11295698301887807297.stgit@bahia.lan> References: <154774526588.1208625.11295698301887807297.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19011717-0012-0000-0000-000002E9634F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19011717-0013-0000-0000-00002120807A Message-Id: <154774530571.1208625.5318753891932747707.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-17_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=936 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901170123 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v3 06/19] spapr: Identify LSIs of all possible PHBs at machine init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Every PHB needs to claim 4 LSIs to support legacy PCI devices. This is currently done at PHB realize. When using in-kernel XICS (or upcoming in-kernel XIVE), QEMU synchronizes the state of all irqs, including these LSIs, later on at machine reset. In order to support PHB hotplug, we need a way to tell KVM about the LSIs that doesn't require a machine reset. Since these irq numbers are fixed values derived from the PHB index, let's identify them all at machine init. Older machines that don't have fixed irq numbers cannot support PHB hotplug and keep the existing behavior. Signed-off-by: Greg Kurz --- hw/ppc/spapr.c | 6 ++++++ hw/ppc/spapr_pci.c | 20 ++++++++++++++++++-- include/hw/pci-host/spapr.h | 2 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 26f8e55cc25e..9189b4d3a9d6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2802,6 +2802,12 @@ static void spapr_machine_init(MachineState *machine) =20 phb =3D spapr_create_default_phb(); =20 + if (!smc->legacy_irq_allocation) { + for (i =3D 0; i < SPAPR_MAX_PHBS; i++) { + spapr_phb_set_lsis(i, spapr); + } + } + for (i =3D 0; i < nb_nics; i++) { NICInfo *nd =3D &nd_table[i]; =20 diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index ec9d4d28004c..f5f13a4d4816 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1559,6 +1559,22 @@ static void spapr_pci_unplug_request(HotplugHandler = *plug_handler, } } =20 +static uint32_t spapr_phb_index_to_lsi(int phb_index, int irq_index) +{ + return SPAPR_IRQ_PCI_LSI + phb_index * PCI_NUM_PINS + irq_index; +} + +void spapr_phb_set_lsis(int index, sPAPRMachineState *spapr) +{ + int i; + + for (i =3D 0; i < PCI_NUM_PINS; i++) { + uint32_t irq =3D spapr_phb_index_to_lsi(index, i); + + spapr_irq_set_type(spapr, irq, true); + } +} + static void spapr_phb_realize(DeviceState *dev, Error **errp) { /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user @@ -1726,7 +1742,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) =20 /* Initialize the LSI table */ for (i =3D 0; i < PCI_NUM_PINS; i++) { - uint32_t irq =3D SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + = i; + uint32_t irq =3D spapr_phb_index_to_lsi(sphb->index, i); Error *local_err =3D NULL; =20 if (smc->legacy_irq_allocation) { @@ -1736,6 +1752,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) "can't allocate LSIs: "); return; } + spapr_irq_set_type(spapr, irq, true); } =20 spapr_irq_claim(spapr, irq, &local_err); @@ -1743,7 +1760,6 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) error_propagate_prepend(errp, local_err, "can't allocate LSIs:= "); return; } - spapr_irq_set_type(spapr, irq, true); =20 sphb->lsi_table[i].irq =3D irq; } diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index e0e683c32469..bb0ae7fdd41d 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -164,4 +164,6 @@ static inline void spapr_phb_vfio_reset(DeviceState *qd= ev) =20 void spapr_phb_dma_reset(sPAPRPHBState *sphb); =20 +void spapr_phb_set_lsis(int index, sPAPRMachineState *spapr); + #endif /* PCI_HOST_SPAPR_H */