From nobody Fri Nov 7 13:05:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547745920660264.8920896283465; Thu, 17 Jan 2019 09:25:20 -0800 (PST) Received: from localhost ([127.0.0.1]:48606 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkBPr-0001WL-IL for importer@patchew.org; Thu, 17 Jan 2019 12:25:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkBFi-0001wL-Jy for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:14:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkBFh-0007GN-GF for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:14:50 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45380 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gkBFh-0007Fj-Al for qemu-devel@nongnu.org; Thu, 17 Jan 2019 12:14:49 -0500 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x0HHEZAj094696 for ; Thu, 17 Jan 2019 12:14:48 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q2wah9p49-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 17 Jan 2019 12:14:48 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 17 Jan 2019 17:14:46 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 17 Jan 2019 17:14:42 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0HHEfud7078322 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Jan 2019 17:14:41 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 18CD752059; Thu, 17 Jan 2019 17:14:41 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id F0A6B5204F; Thu, 17 Jan 2019 17:14:40 +0000 (GMT) Received: from bahia.lan (sig-9-145-42-56.uk.ibm.com [9.145.42.56]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C4BE8220129; Thu, 17 Jan 2019 18:14:39 +0100 (CET) From: Greg Kurz To: David Gibson Date: Thu, 17 Jan 2019 18:14:39 +0100 In-Reply-To: <154774526588.1208625.11295698301887807297.stgit@bahia.lan> References: <154774526588.1208625.11295698301887807297.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-TM-AS-GCONF: 00 x-cbid: 19011717-4275-0000-0000-000003008FC3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19011717-4276-0000-0000-0000380EB56A Message-Id: <154774527936.1208625.3070534654296462659.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-17_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901170123 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x0HHEZAj094696 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v3 02/19] spapr: Rename xics to intc in interrupt controller agnostic code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" All this code is used with both the XICS and XIVE interrupt controllers. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- v3: - s/spapr_dt_intc_irq/spapr_dt_irq --- hw/ppc/spapr.c | 6 +++--- hw/ppc/spapr_events.c | 2 +- hw/ppc/spapr_pci.c | 6 +++--- hw/ppc/spapr_vio.c | 2 +- include/hw/pci-host/spapr.h | 2 +- include/hw/ppc/spapr.h | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 83081defde4e..26f8e55cc25e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -96,7 +96,7 @@ =20 #define MIN_RMA_SLOF 128UL =20 -#define PHANDLE_XICP 0x00001111 +#define PHANDLE_INTC 0x00001111 =20 /* These two functions implement the VCPU id numbering: one to compute them * all and one to identify thread 0 of a VCORE. Any change to the first one @@ -1276,7 +1276,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, =20 /* /interrupt controller */ spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, - PHANDLE_XICP); + PHANDLE_INTC); =20 ret =3D spapr_populate_memory(spapr, fdt); if (ret < 0) { @@ -1296,7 +1296,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, } =20 QLIST_FOREACH(phb, &spapr->phbs, list) { - ret =3D spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, + ret =3D spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis); if (ret < 0) { error_report("couldn't setup PCI devices in fdt"); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 32719a1b72d0..b9c7ecb9e987 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -282,7 +282,7 @@ void spapr_dt_events(sPAPRMachineState *spapr, void *fd= t) continue; } =20 - spapr_dt_xics_irq(interrupts, source->irq, false); + spapr_dt_irq(interrupts, source->irq, false); =20 _FDT(node_offset =3D fdt_add_subnode(fdt, event_sources, source_na= me)); _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index b74f2632ecc6..ccdaf2c9a606 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2066,7 +2066,7 @@ static void spapr_phb_pci_enumerate(sPAPRPHBState *ph= b) =20 } =20 -int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void = *fdt, +int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void = *fdt, uint32_t nr_msis) { int bus_off, i, j, ret; @@ -2164,8 +2164,8 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_= t xics_phandle, void *fdt, irqmap[1] =3D 0; irqmap[2] =3D 0; irqmap[3] =3D cpu_to_be32(j+1); - irqmap[4] =3D cpu_to_be32(xics_phandle); - spapr_dt_xics_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, tru= e); + irqmap[4] =3D cpu_to_be32(intc_phandle); + spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); } } /* Write interrupt map */ diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 7e8a9ad09337..f80b70a39c46 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -158,7 +158,7 @@ static int vio_make_devnode(VIOsPAPRDevice *dev, if (dev->irq) { uint32_t ints_prop[2]; =20 - spapr_dt_xics_irq(ints_prop, dev->irq, false); + spapr_dt_irq(ints_prop, dev->irq, false); ret =3D fdt_setprop(fdt, node_off, "interrupts", ints_prop, sizeof(ints_prop)); if (ret < 0) { diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 4eb3a2ce3eb8..e0e683c32469 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -113,7 +113,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRP= HBState *phb, int pin) return spapr_qirq(spapr, phb->lsi_table[pin].irq); } =20 -int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void = *fdt, +int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void = *fdt, uint32_t nr_msis); =20 void spapr_pci_rtas_init(void); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9e01a5a12e4a..f988dc6924b8 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -682,7 +682,7 @@ void spapr_load_rtas(sPAPRMachineState *spapr, void *fd= t, hwaddr addr); * "interrupt-controller" node has its "#interrupt-cells" property set to = 2 (ie, * VIO devices, RTAS event sources and PHBs). */ -static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_l= si) +static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) { intspec[0] =3D cpu_to_be32(irq); intspec[1] =3D is_lsi ? cpu_to_be32(1) : 0;