From nobody Fri Nov 7 09:22:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440974111382.68125955852645; Sun, 13 Jan 2019 20:42:54 -0800 (PST) Received: from localhost ([127.0.0.1]:57381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu5M-0002aS-NG for importer@patchew.org; Sun, 13 Jan 2019 23:42:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu0B-0007g9-KU for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giu01-0002ag-VG for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:25 -0500 Received: from mga05.intel.com ([192.55.52.43]:15387) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gitzz-0002SG-Fs for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:21 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:08 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:06 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554091" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:58 +0800 Message-Id: <1547468699-17633-5-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 4/5] i386: enable CPUID.1F leaf generation based on spec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch uses the new socket/die/core/thread model to generate cpuid.1f eax/ebx/ecx/edx values especially the subleaf 2 which keeps die level information and adds an option in the cpu_x86_cpuid. Signed-off-by: Like Xu --- target/i386/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fa37203..85f9074 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4137,7 +4137,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D x86_env_get_cpu(env); CPUState *cs =3D CPU(cpu); - uint32_t pkg_offset; + uint32_t die_offset; uint32_t limit; uint32_t signature[3]; =20 @@ -4152,7 +4152,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, limit =3D env->cpuid_level; } =20 - if (index > limit) { + if (index > limit && index !=3D 0x1F) { /* Intel documentation states that invalid EAX input will * return the same information as EAX=3Dcpuid_level * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) @@ -4226,10 +4226,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - pkg_offset =3D apicid_pkg_offset(cs->nr_cores, cs->nr_thre= ads); + die_offset =3D apicid_die_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads= ); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << pkg_offset), cs->nr_cores, + (1 << die_offset), cs->nr_cores, eax, ebx, ecx, edx); break; } @@ -4311,12 +4312,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: - *eax =3D apicid_core_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_core_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_pkg_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4325,7 +4328,46 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D 0; *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; } + assert(!(*eax & ~0x1f)); + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + break; + case 0x1F: + if (cs->nr_dies > 1 && !cpu->enable_cpuid_0x1f) { + printf("Host CPU may not use multi-chip packaging technology.\= n"); + exit(0); + } =20 + if (cs->nr_dies < 2) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + switch (count) { + case 0: + *eax =3D apicid_core_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_die_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + case 2: + *eax =3D apicid_pkg_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_dies * cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; @@ -5709,11 +5751,13 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), @@ -5748,6 +5792,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), + DEFINE_PROP_BOOL("cpuid-0x1f", X86CPU, enable_cpuid_0x1f, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, --=20 1.8.3.1