From nobody Fri Nov 7 07:08:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440760753438.49379695909374; Sun, 13 Jan 2019 20:39:20 -0800 (PST) Received: from localhost ([127.0.0.1]:56415 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu1r-0008UE-Mk for importer@patchew.org; Sun, 13 Jan 2019 23:39:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40707) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu01-0007bP-Cd for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gitzt-0002X4-5z for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:16 -0500 Received: from mga05.intel.com ([192.55.52.43]:15387) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gitzp-0002SG-S2 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:10 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:02 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:00 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554071" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:55 +0800 Message-Id: <1547468699-17633-2-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 1/5] cpu: introduce die, the new cpu toppolgy emulation level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Following codes on smp_cores, the smp_dies/nr_dies/die-id is added to machine and CPUState. In addition to enable_cpuid_0xb, enable_cpuid_0x1f is introduced to track wether host is a new MCP macine or just ignored. The number for die level_type on Intel is 5 while core type keeps 2. Signed-off-by: Like Xu --- cpus.c | 1 + include/qom/cpu.h | 1 + include/sysemu/cpus.h | 1 + qapi/misc.json | 1 + target/i386/cpu.h | 5 +++++ 5 files changed, 9 insertions(+) diff --git a/cpus.c b/cpus.c index b09b702..503558d 100644 --- a/cpus.c +++ b/cpus.c @@ -2066,6 +2066,7 @@ static void qemu_dummy_start_vcpu(CPUState *cpu) =20 void qemu_init_vcpu(CPUState *cpu) { + cpu->nr_dies =3D smp_dies; cpu->nr_cores =3D smp_cores; cpu->nr_threads =3D smp_threads; cpu->stopped =3D true; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 16bbed1..ee53862 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -332,6 +332,7 @@ struct CPUState { DeviceState parent_obj; /*< public >*/ =20 + int nr_dies; int nr_cores; int nr_threads; =20 diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index 731756d..4243c8f 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -34,6 +34,7 @@ void qtest_clock_warp(int64_t dest); #ifndef CONFIG_USER_ONLY /* vl.c */ /* *-user doesn't have configurable SMP topology */ +extern int smp_dies; extern int smp_cores; extern int smp_threads; #endif diff --git a/qapi/misc.json b/qapi/misc.json index 24d20a8..a01a9fe 100644 --- a/qapi/misc.json +++ b/qapi/misc.json @@ -3229,6 +3229,7 @@ { 'struct': 'CpuInstanceProperties', 'data': { '*node-id': 'int', '*socket-id': 'int', + '*die-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ef41a03..aa2ee8a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -732,6 +732,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) +#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) @@ -1450,6 +1451,9 @@ struct X86CPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; =20 + /* Compatibility bits for new machine types: */ + bool enable_cpuid_0x1f; + /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; =20 @@ -1475,6 +1479,7 @@ struct X86CPU { =20 int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; + int32_t die_id; int32_t core_id; int32_t thread_id; =20 --=20 1.8.3.1 From nobody Fri Nov 7 07:08:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440759284654.1515843538191; Sun, 13 Jan 2019 20:39:19 -0800 (PST) Received: from localhost ([127.0.0.1]:56350 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu1b-0008HU-Is for importer@patchew.org; Sun, 13 Jan 2019 23:38:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40687) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gitzt-0007YU-MM for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gitzq-0002WI-FL for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:11 -0500 Received: from mga05.intel.com ([192.55.52.43]:15389) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gitzo-0002TQ-16 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:09 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:04 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:02 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554079" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:56 +0800 Message-Id: <1547468699-17633-3-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 2/5] vl.c: add -smp, dies=* command line support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch updates the check rules on legeacy -smp parse from user command and it's designed to obey the same restrictions as socket/core/thread model. Signed-off-by: Like Xu --- hmp.c | 3 +++ hw/core/machine.c | 12 ++++++++++++ vl.c | 33 ++++++++++++++++++++------------- 3 files changed, 35 insertions(+), 13 deletions(-) diff --git a/hmp.c b/hmp.c index 80aa5ab..05ac133 100644 --- a/hmp.c +++ b/hmp.c @@ -3013,6 +3013,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict = *qdict) if (c->has_socket_id) { monitor_printf(mon, " socket-id: \"%" PRIu64 "\"\n", c->soc= ket_id); } + if (c->has_die_id) { + monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id= ); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_= id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index 95dc7c3..05bc545 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -601,6 +601,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } =20 + if (props->has_die_id && !slot->props.has_die_id) { + error_setg(errp, "die-id is not supported"); + return; + } + if (props->has_socket_id && !slot->props.has_socket_id) { error_setg(errp, "socket-id is not supported"); return; @@ -615,6 +620,10 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } =20 + if (props->has_die_id && props->die_id !=3D slot->props.die_id) { + continue; + } + if (props->has_socket_id && props->socket_id !=3D slot->props.sock= et_id) { continue; } @@ -849,6 +858,9 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) if (cpu->props.has_socket_id) { g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_= id); } + if (cpu->props.has_die_id) { + g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); diff --git a/vl.c b/vl.c index 9b8ea3f..72be689 100644 --- a/vl.c +++ b/vl.c @@ -169,6 +169,7 @@ int win2k_install_hack =3D 0; int singlestep =3D 0; int smp_cpus; unsigned int max_cpus; +int smp_dies =3D 1; int smp_cores =3D 1; int smp_threads =3D 1; int acpi_enabled =3D 1; @@ -1208,6 +1209,9 @@ static QemuOptsList qemu_smp_opts =3D { .name =3D "sockets", .type =3D QEMU_OPT_NUMBER, }, { + .name =3D "dies", + .type =3D QEMU_OPT_NUMBER, + }, { .name =3D "cores", .type =3D QEMU_OPT_NUMBER, }, { @@ -1226,32 +1230,34 @@ static void smp_parse(QemuOpts *opts) if (opts) { unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); + unsigned dies =3D qemu_opt_get_number(opts, "dies", 0); unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); =20 /* compute missing values, prefer sockets over cores over threads = */ + dies =3D dies > 0 ? dies : 1; if (cpus =3D=3D 0 || sockets =3D=3D 0) { cores =3D cores > 0 ? cores : 1; threads =3D threads > 0 ? threads : 1; if (cpus =3D=3D 0) { sockets =3D sockets > 0 ? sockets : 1; - cpus =3D cores * threads * sockets; + cpus =3D cores * threads * dies * sockets; } else { max_cpus =3D qemu_opt_get_number(opts, "maxcpus", cpus); - sockets =3D max_cpus / (cores * threads); + sockets =3D max_cpus / (cores * threads * dies); } } else if (cores =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - cores =3D cpus / (sockets * threads); + cores =3D cpus / (sockets * dies * threads); cores =3D cores > 0 ? cores : 1; } else if (threads =3D=3D 0) { - threads =3D cpus / (cores * sockets); + threads =3D cpus / (cores * dies * sockets); threads =3D threads > 0 ? threads : 1; - } else if (sockets * cores * threads < cpus) { + } else if (sockets * dies * cores * threads < cpus) { error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) < " + "sockets (%u) * dies (%u) * cores (%u) * threads = (%u) < " "smp_cpus (%u)", - sockets, cores, threads, cpus); + sockets, dies, cores, threads, cpus); exit(1); } =20 @@ -1262,22 +1268,23 @@ static void smp_parse(QemuOpts *opts) exit(1); } =20 - if (sockets * cores * threads > max_cpus) { + if (sockets * dies * cores * threads > max_cpus) { error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) > " + "sockets (%u) * dies (%u) * cores (%u) * threads = (%u) > " "maxcpus (%u)", - sockets, cores, threads, max_cpus); + sockets, dies, cores, threads, max_cpus); exit(1); } =20 - if (sockets * cores * threads !=3D max_cpus) { + if (sockets * dies * cores * threads !=3D max_cpus) { warn_report("Invalid CPU topology deprecated: " - "sockets (%u) * cores (%u) * threads (%u) " + "sockets (%u) * dies (%u) * cores (%u) * threads (= %u) " "!=3D maxcpus (%u)", - sockets, cores, threads, max_cpus); + sockets, dies, cores, threads, max_cpus); } =20 smp_cpus =3D cpus; + smp_dies =3D dies; smp_cores =3D cores; smp_threads =3D threads; } --=20 1.8.3.1 From nobody Fri Nov 7 07:08:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440897410168.48406763676235; Sun, 13 Jan 2019 20:41:37 -0800 (PST) Received: from localhost ([127.0.0.1]:57048 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu48-0001oZ-D7 for importer@patchew.org; Sun, 13 Jan 2019 23:41:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40721) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu01-0007bR-TU for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gitzz-0002ZH-GM for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:21 -0500 Received: from mga05.intel.com ([192.55.52.43]:15389) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gitzt-0002TQ-Mg for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:15 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:06 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:04 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554084" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:57 +0800 Message-Id: <1547468699-17633-4-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 3/5] i386: extend x86_apicid_* functions for smp_dies support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch rewrites the width/offset-apicid calculation with compatibility. It keeps the original symmetry as a default method and sets the die_id as well as node_id for leageacy numde_node auto-configuration. Signed-off-by: Like Xu --- hw/i386/pc.c | 37 +++++++++++++++------- include/hw/i386/topology.h | 79 ++++++++++++++++++++++++++++++++++--------= ---- 2 files changed, 84 insertions(+), 32 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index fc65049..2f01886 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -909,7 +909,8 @@ static uint32_t x86_cpu_apic_id_from_index(unsigned int= cpu_index) uint32_t correct_id; static bool warned; =20 - correct_id =3D x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_ind= ex); + correct_id =3D x86_apicid_from_cpu_idx(smp_dies, smp_cores, + smp_threads, cpu_index); if (compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -2137,9 +2138,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, return; } =20 - /* if APIC ID is not set, set it based on socket/core/thread propertie= s */ + /* + * If APIC ID is not set, set it based on + * socket/die/core/thread properties. + */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (max_cpus - 1) / smp_threads / smp_cores; + int max_socket =3D (max_cpus - 1) / smp_threads / smp_cores / smp_= dies; =20 if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); @@ -2148,6 +2152,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, error_setg(errp, "Invalid CPU socket-id: %u must be in range 0= :%u", cpu->socket_id, max_socket); return; + } else if (cpu->die_id > max_socket) { + error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u= ", + cpu->die_id, max_socket); + return; } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); @@ -2167,20 +2175,24 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, } =20 topo.pkg_id =3D cpu->socket_id; + topo.die_id =3D cpu->die_id; topo.core_id =3D cpu->core_id; topo.smt_id =3D cpu->thread_id; - cpu->apic_id =3D apicid_from_topo_ids(smp_cores, smp_threads, &top= o); + cpu->apic_id =3D apicid_from_topo_ids(smp_dies, smp_cores, + smp_threads, &topo); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &to= po); - error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] w= ith" + x86_topo_ids_from_apicid(cpu->apic_id, smp_dies, smp_cores, + smp_threads, &topo); + error_setg(errp, + "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u]= with" " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, - ms->possible_cpus->len - 1); + topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + cpu->apic_id, ms->possible_cpus->len - 1); return; } =20 @@ -2196,7 +2208,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); + x86_topo_ids_from_apicid(cpu->apic_id, + smp_dies, smp_cores, smp_threads, &topo); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pk= g_id); @@ -2529,7 +2542,7 @@ static int64_t pc_get_default_cpu_node_id(const Machi= neState *ms, int idx) =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - smp_cores, smp_threads, &topo); + smp_dies, smp_cores, smp_threads, &topo); return topo.pkg_id % nb_numa_nodes; } =20 @@ -2556,9 +2569,11 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids= (MachineState *ms) ms->possible_cpus->cpus[i].vcpus_count =3D 1; ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - smp_cores, smp_threads, &topo); + smp_dies, smp_cores, smp_threads, &topo); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; + ms->possible_cpus->cpus[i].props.has_die_id =3D true; + ms->possible_cpus->cpus[i].props.die_id =3D topo.die_id; ms->possible_cpus->cpus[i].props.has_core_id =3D true; ms->possible_cpus->cpus[i].props.core_id =3D topo.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 1ebaee0..1e344db 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -47,6 +47,8 @@ typedef uint32_t apic_id_t; =20 typedef struct X86CPUTopoInfo { unsigned pkg_id; + unsigned node_id; + unsigned die_id; unsigned core_id; unsigned smt_id; } X86CPUTopoInfo; @@ -62,87 +64,122 @@ static unsigned apicid_bitwidth_for_count(unsigned cou= nt) =20 /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_cores, unsigned nr_thr= eads) +static inline unsigned apicid_smt_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_threads); } =20 /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_core_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_cores); } =20 +/* Bit width of the Die_ID field */ +static inline unsigned apicid_die_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_bitwidth_for_count(nr_dies); +} + /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_cores, +static inline unsigned apicid_core_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_smt_width(nr_dies, nr_cores, nr_threads); +} + +/* Bit offset of the Die_ID field */ +static inline unsigned apicid_die_offset(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads) { - return apicid_smt_width(nr_cores, nr_threads); + return apicid_core_offset(nr_dies, nr_cores, nr_threads) + + apicid_core_width(nr_dies, nr_cores, nr_threads); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_pkg_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { - return apicid_core_offset(nr_cores, nr_threads) + - apicid_core_width(nr_cores, nr_threads); + return apicid_die_offset(nr_dies, nr_cores, nr_threads) + + apicid_die_width(nr_dies, nr_cores, nr_threads); } =20 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores, +static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, const X86CPUTopoInfo *topo) { - return (topo->pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) | - (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) | + return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threa= ds)) | topo->smt_id; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_cores, +static inline void x86_topo_ids_from_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, X86CPUTopoInfo *topo) { - unsigned core_index =3D cpu_index / nr_threads; + topo->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo->node_id =3D cpu_index / (nr_cores * nr_threads); + topo->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo->core_id =3D cpu_index / nr_threads % nr_cores; topo->smt_id =3D cpu_index % nr_threads; - topo->core_id =3D core_index % nr_cores; - topo->pkg_id =3D core_index / nr_cores; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, + unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, X86CPUTopoInfo *topo) { topo->smt_id =3D apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_cores, nr_threads= )); - topo->core_id =3D (apicid >> apicid_core_offset(nr_cores, nr_threads))= & - ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_thread= s)); - topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_cores, nr_threads); + ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); + topo->core_id =3D + (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_thre= ads)); + topo->die_id =3D + (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threa= ds)); + topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_thr= eads); + topo->node_id =3D apicid / (nr_cores * nr_threads); } =20 /* Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores, +static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index) { X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_cores, nr_threads, &topo); + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); } =20 #endif /* HW_I386_TOPOLOGY_H */ --=20 1.8.3.1 From nobody Fri Nov 7 07:08:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440974111382.68125955852645; Sun, 13 Jan 2019 20:42:54 -0800 (PST) Received: from localhost ([127.0.0.1]:57381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu5M-0002aS-NG for importer@patchew.org; Sun, 13 Jan 2019 23:42:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu0B-0007g9-KU for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giu01-0002ag-VG for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:25 -0500 Received: from mga05.intel.com ([192.55.52.43]:15387) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gitzz-0002SG-Fs for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:21 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:08 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:06 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554091" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:58 +0800 Message-Id: <1547468699-17633-5-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 4/5] i386: enable CPUID.1F leaf generation based on spec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch uses the new socket/die/core/thread model to generate cpuid.1f eax/ebx/ecx/edx values especially the subleaf 2 which keeps die level information and adds an option in the cpu_x86_cpuid. Signed-off-by: Like Xu --- target/i386/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fa37203..85f9074 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4137,7 +4137,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D x86_env_get_cpu(env); CPUState *cs =3D CPU(cpu); - uint32_t pkg_offset; + uint32_t die_offset; uint32_t limit; uint32_t signature[3]; =20 @@ -4152,7 +4152,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, limit =3D env->cpuid_level; } =20 - if (index > limit) { + if (index > limit && index !=3D 0x1F) { /* Intel documentation states that invalid EAX input will * return the same information as EAX=3Dcpuid_level * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) @@ -4226,10 +4226,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - pkg_offset =3D apicid_pkg_offset(cs->nr_cores, cs->nr_thre= ads); + die_offset =3D apicid_die_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads= ); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << pkg_offset), cs->nr_cores, + (1 << die_offset), cs->nr_cores, eax, ebx, ecx, edx); break; } @@ -4311,12 +4312,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: - *eax =3D apicid_core_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_core_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_pkg_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4325,7 +4328,46 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D 0; *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; } + assert(!(*eax & ~0x1f)); + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + break; + case 0x1F: + if (cs->nr_dies > 1 && !cpu->enable_cpuid_0x1f) { + printf("Host CPU may not use multi-chip packaging technology.\= n"); + exit(0); + } =20 + if (cs->nr_dies < 2) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + switch (count) { + case 0: + *eax =3D apicid_core_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_die_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + case 2: + *eax =3D apicid_pkg_offset(cs->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_dies * cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; @@ -5709,11 +5751,13 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), @@ -5748,6 +5792,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), + DEFINE_PROP_BOOL("cpuid-0x1f", X86CPU, enable_cpuid_0x1f, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, --=20 1.8.3.1 From nobody Fri Nov 7 07:08:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547440768902330.6965726782388; Sun, 13 Jan 2019 20:39:28 -0800 (PST) Received: from localhost ([127.0.0.1]:56455 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu23-00009w-OM for importer@patchew.org; Sun, 13 Jan 2019 23:39:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giu0D-0007hG-0M for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giu0B-0002f9-LQ for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:32 -0500 Received: from mga05.intel.com ([192.55.52.43]:15389) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1giu02-0002TQ-3Q for qemu-devel@nongnu.org; Sun, 13 Jan 2019 23:37:25 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jan 2019 20:37:09 -0800 Received: from xulike-server.sh.intel.com ([10.239.48.60]) by fmsmga005.fm.intel.com with ESMTP; 13 Jan 2019 20:37:08 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,476,1539673200"; d="scan'208";a="311554096" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 20:24:59 +0800 Message-Id: <1547468699-17633-6-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> References: <1547468699-17633-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 5/5] i386: add CPUID.1F to cpuid_data with host_cpuid check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, Peter Crosthwaite , Eduardo Habkost , "Michael S. Tsirkin" , like.xu@intel.com, Marcelo Tosatti , Paolo Bonzini , imammedo@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When cs->nr_dies is larger than 1, the CPUID.1F should be generated and is added to cpuid_data.entries for guest awareness. This patch provides a return option in kvm_has_cpuid_1f for default choice. Signed-off-by: Like Xu --- target/i386/kvm.c | 34 +++++++++++++++++++++++++++++++++- target/i386/kvm_i386.h | 1 + 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 739cf8c..eb0d1ee 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -120,6 +120,17 @@ bool kvm_has_smm(void) return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM); } =20 +bool kvm_has_cpuid_1f(void) +{ + uint32_t eax =3D 0x1f, ecx =3D 1, ebx =3D 0, edx =3D 0; + host_cpuid(0x1f, 0, &eax, &ebx, &ecx, &edx); + if (eax !=3D 0) { + printf("It's recommended to disable CPUID.1F emulation \ + on Intel non-MCP platform.\n"); + } + return true; +} + bool kvm_has_adjust_clock_stable(void) { int ret =3D kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); @@ -1035,7 +1046,6 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); - for (i =3D 0; i <=3D limit; i++) { if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { fprintf(stderr, "unsupported level value: 0x%x\n", limit); @@ -1127,6 +1137,28 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 + cpu->enable_cpuid_0x1f =3D kvm_has_cpuid_1f(); + if (cs->nr_dies > 1) { + i =3D 0x1f; + for (j =3D 0; ; j++) { + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index =3D j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); + if (i =3D=3D 0x1f && j =3D=3D 3) { + break; + } + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c =3D &cpuid_data.entries[cpuid_i++]; + if (!cpu->enable_cpuid_0x1f) + break; + } + } + if (limit >=3D 0x0a) { uint32_t eax, edx; =20 diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h index 3057ba4..ef9d41e 100644 --- a/target/i386/kvm_i386.h +++ b/target/i386/kvm_i386.h @@ -38,6 +38,7 @@ bool kvm_has_adjust_clock_stable(void); void kvm_synchronize_all_tsc(void); void kvm_arch_reset_vcpu(X86CPU *cs); void kvm_arch_do_init_vcpu(X86CPU *cs); +bool kvm_has_cpuid_1f(void); =20 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, uint32_t flags, uint32_t *dev_id); --=20 1.8.3.1