From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533635688871.9834809161132; Thu, 3 Jan 2019 08:40:35 -0800 (PST) Received: from localhost ([127.0.0.1]:55907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf62s-0006A5-IP for importer@patchew.org; Thu, 03 Jan 2019 11:40:34 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5y6-0001Lg-Of for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5y5-0007xw-Op for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:38 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:40396 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5y5-0006vn-DC for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:37 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 43F351A2037; Thu, 3 Jan 2019 17:34:35 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2724A1A1529; Thu, 3 Jan 2019 17:34:35 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:05 +0100 Message-Id: <1546533252-26601-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 1/8] target/mips: Move comment containing summary of CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Move comment containing summary of CP0 registers. Checkpatch script reported some tabs in the resutling diff, so convert these tabs to spaces too. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/cpu.h | 165 +++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 84 insertions(+), 81 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 03c03fd..6c2a7e4 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -123,87 +123,6 @@ typedef struct mips_def_t mips_def_t; #define MIPS_KSCRATCH_NUM 6 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ =20 -typedef struct TCState TCState; -struct TCState { - target_ulong gpr[32]; - target_ulong PC; - target_ulong HI[MIPS_DSP_ACC]; - target_ulong LO[MIPS_DSP_ACC]; - target_ulong ACX[MIPS_DSP_ACC]; - target_ulong DSPControl; - int32_t CP0_TCStatus; -#define CP0TCSt_TCU3 31 -#define CP0TCSt_TCU2 30 -#define CP0TCSt_TCU1 29 -#define CP0TCSt_TCU0 28 -#define CP0TCSt_TMX 27 -#define CP0TCSt_RNST 23 -#define CP0TCSt_TDS 21 -#define CP0TCSt_DT 20 -#define CP0TCSt_DA 15 -#define CP0TCSt_A 13 -#define CP0TCSt_TKSU 11 -#define CP0TCSt_IXMT 10 -#define CP0TCSt_TASID 0 - int32_t CP0_TCBind; -#define CP0TCBd_CurTC 21 -#define CP0TCBd_TBE 17 -#define CP0TCBd_CurVPE 0 - target_ulong CP0_TCHalt; - target_ulong CP0_TCContext; - target_ulong CP0_TCSchedule; - target_ulong CP0_TCScheFBack; - int32_t CP0_Debug_tcstatus; - target_ulong CP0_UserLocal; - - int32_t msacsr; - -#define MSACSR_FS 24 -#define MSACSR_FS_MASK (1 << MSACSR_FS) -#define MSACSR_NX 18 -#define MSACSR_NX_MASK (1 << MSACSR_NX) -#define MSACSR_CEF 2 -#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) -#define MSACSR_RM 0 -#define MSACSR_RM_MASK (0x3 << MSACSR_RM) -#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK= | \ - MSACSR_FS_MASK) - - float_status msa_fp_status; - -#define NUMBER_OF_MXU_REGISTERS 16 - target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; - target_ulong mxu_cr; -#define MXU_CR_LC 31 -#define MXU_CR_RC 30 -#define MXU_CR_BIAS 2 -#define MXU_CR_RD_EN 1 -#define MXU_CR_MXU_EN 0 - -}; - -typedef struct CPUMIPSState CPUMIPSState; -struct CPUMIPSState { - TCState active_tc; - CPUMIPSFPUContext active_fpu; - - uint32_t current_tc; - uint32_t current_fpu; - - uint32_t SEGBITS; - uint32_t PABITS; -#if defined(TARGET_MIPS64) -# define PABITS_BASE 36 -#else -# define PABITS_BASE 32 -#endif - target_ulong SEGMask; - uint64_t PAMask; -#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) - - int32_t msair; -#define MSAIR_ProcID 8 -#define MSAIR_Rev 0 =20 /* * Summary of CP0 registers @@ -314,6 +233,90 @@ struct CPUMIPSState { * 7 TagLo TagHi KScratch * */ + + +typedef struct TCState TCState; +struct TCState { + target_ulong gpr[32]; + target_ulong PC; + target_ulong HI[MIPS_DSP_ACC]; + target_ulong LO[MIPS_DSP_ACC]; + target_ulong ACX[MIPS_DSP_ACC]; + target_ulong DSPControl; + int32_t CP0_TCStatus; +#define CP0TCSt_TCU3 31 +#define CP0TCSt_TCU2 30 +#define CP0TCSt_TCU1 29 +#define CP0TCSt_TCU0 28 +#define CP0TCSt_TMX 27 +#define CP0TCSt_RNST 23 +#define CP0TCSt_TDS 21 +#define CP0TCSt_DT 20 +#define CP0TCSt_DA 15 +#define CP0TCSt_A 13 +#define CP0TCSt_TKSU 11 +#define CP0TCSt_IXMT 10 +#define CP0TCSt_TASID 0 + int32_t CP0_TCBind; +#define CP0TCBd_CurTC 21 +#define CP0TCBd_TBE 17 +#define CP0TCBd_CurVPE 0 + target_ulong CP0_TCHalt; + target_ulong CP0_TCContext; + target_ulong CP0_TCSchedule; + target_ulong CP0_TCScheFBack; + int32_t CP0_Debug_tcstatus; + target_ulong CP0_UserLocal; + + int32_t msacsr; + +#define MSACSR_FS 24 +#define MSACSR_FS_MASK (1 << MSACSR_FS) +#define MSACSR_NX 18 +#define MSACSR_NX_MASK (1 << MSACSR_NX) +#define MSACSR_CEF 2 +#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) +#define MSACSR_RM 0 +#define MSACSR_RM_MASK (0x3 << MSACSR_RM) +#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK= | \ + MSACSR_FS_MASK) + + float_status msa_fp_status; + +#define NUMBER_OF_MXU_REGISTERS 16 + target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; + target_ulong mxu_cr; +#define MXU_CR_LC 31 +#define MXU_CR_RC 30 +#define MXU_CR_BIAS 2 +#define MXU_CR_RD_EN 1 +#define MXU_CR_MXU_EN 0 + +}; + +typedef struct CPUMIPSState CPUMIPSState; +struct CPUMIPSState { + TCState active_tc; + CPUMIPSFPUContext active_fpu; + + uint32_t current_tc; + uint32_t current_fpu; + + uint32_t SEGBITS; + uint32_t PABITS; +#if defined(TARGET_MIPS64) +# define PABITS_BASE 36 +#else +# define PABITS_BASE 32 +#endif + target_ulong SEGMask; + uint64_t PAMask; +#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) + + int32_t msair; +#define MSAIR_ProcID 8 +#define MSAIR_Rev 0 + /* * CP0 Register 0 */ --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533760000897.9848718744289; Thu, 3 Jan 2019 08:42:40 -0800 (PST) Received: from localhost ([127.0.0.1]:55929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf64s-0008Vg-V6 for importer@patchew.org; Thu, 03 Jan 2019 11:42:38 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5yG-0001WK-3K for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5yA-00082n-VZ for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:47 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:40574 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5yA-00070c-OK for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D5D281A2074; Thu, 3 Jan 2019 17:34:40 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id BCDB31A1529; Thu, 3 Jan 2019 17:34:40 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:06 +0100 Message-Id: <1546533252-26601-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add preprocessor constants for 32 major CP0 registers. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/cpu.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6c2a7e4..b095422 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t; * 7 TagLo TagHi KScratch * */ +#define CPO_REGISTER_00 0 +#define CPO_REGISTER_01 1 +#define CPO_REGISTER_02 2 +#define CPO_REGISTER_03 3 +#define CPO_REGISTER_04 4 +#define CPO_REGISTER_05 5 +#define CPO_REGISTER_06 6 +#define CPO_REGISTER_07 7 +#define CPO_REGISTER_08 8 +#define CPO_REGISTER_09 9 +#define CPO_REGISTER_10 10 +#define CPO_REGISTER_11 11 +#define CPO_REGISTER_12 12 +#define CPO_REGISTER_13 13 +#define CPO_REGISTER_14 14 +#define CPO_REGISTER_15 15 +#define CPO_REGISTER_16 16 +#define CPO_REGISTER_17 17 +#define CPO_REGISTER_18 18 +#define CPO_REGISTER_19 19 +#define CPO_REGISTER_20 20 +#define CPO_REGISTER_21 21 +#define CPO_REGISTER_22 22 +#define CPO_REGISTER_23 23 +#define CPO_REGISTER_24 24 +#define CPO_REGISTER_25 25 +#define CPO_REGISTER_26 26 +#define CPO_REGISTER_27 27 +#define CPO_REGISTER_28 28 +#define CPO_REGISTER_29 29 +#define CPO_REGISTER_30 30 +#define CPO_REGISTER_31 31 =20 =20 typedef struct TCState TCState; --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=listsout.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from listsout.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546533938466753.2435434431928; Thu, 3 Jan 2019 08:45:38 -0800 (PST) Received: from localhost ([127.0.0.1]:55954 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf67g-0003ER-3x for importer@patchew.org; Thu, 03 Jan 2019 11:45:32 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5yI-0001aF-EU for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5yF-0008BN-7J for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:50 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:40691 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5yE-00072d-Mx for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:47 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B2AB51A2117; Thu, 3 Jan 2019 17:34:44 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8C85F1A1529; Thu, 3 Jan 2019 17:34:44 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:07 +0100 Message-Id: <1546533252-26601-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 3/8] target/mips: Use preprocessor constants for 32 major CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Use preprocessor constants for 32 major CP0 registers. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 272 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 136 insertions(+), 136 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e9c23a5..6af292f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6476,7 +6476,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *rn =3D "invalid"; =20 switch (reg) { - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6487,7 +6487,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6498,7 +6498,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr), @@ -6514,7 +6514,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -6544,7 +6544,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) uint64_t mask =3D ctx->PAMask >> 36; =20 switch (reg) { - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6556,7 +6556,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6568,7 +6568,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: /* LLAddr is read-only (the only exception is bit 0 if LLB is @@ -6586,7 +6586,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -6626,7 +6626,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) check_insn(ctx, ISA_MIPS32); =20 switch (reg) { - case 0: + case CPO_REGISTER_00: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); @@ -6656,7 +6656,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 1: + case CPO_REGISTER_01: switch (sel) { case 0: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); @@ -6702,7 +6702,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: { @@ -6760,7 +6760,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: { @@ -6788,7 +6788,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 4: + case CPO_REGISTER_04: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context= )); @@ -6810,7 +6810,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 5: + case CPO_REGISTER_05: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); @@ -6858,7 +6858,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 6: + case CPO_REGISTER_06: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); @@ -6898,7 +6898,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 7: + case CPO_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -6909,7 +6909,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 8: + case CPO_REGISTER_08: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); @@ -6936,7 +6936,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 9: + case CPO_REGISTER_09: switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ @@ -6959,7 +6959,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 10: + case CPO_REGISTER_10: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); @@ -6970,7 +6970,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 11: + case CPO_REGISTER_11: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); @@ -6981,7 +6981,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 12: + case CPO_REGISTER_12: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); @@ -7006,7 +7006,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 13: + case CPO_REGISTER_13: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); @@ -7016,7 +7016,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 14: + case CPO_REGISTER_14: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -7027,7 +7027,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 15: + case CPO_REGISTER_15: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); @@ -7050,7 +7050,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 16: + case CPO_REGISTER_16: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); @@ -7089,7 +7089,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: gen_helper_mfc0_lladdr(arg, cpu_env); @@ -7109,7 +7109,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 18: + case CPO_REGISTER_18: switch (sel) { case 0: case 1: @@ -7127,7 +7127,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 19: + case CPO_REGISTER_19: switch (sel) { case 0: case 1: @@ -7145,7 +7145,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 20: + case CPO_REGISTER_20: switch (sel) { case 0: #if defined(TARGET_MIPS64) @@ -7159,7 +7159,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 21: + case CPO_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -7171,11 +7171,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; - case 22: + case CPO_REGISTER_22: tcg_gen_movi_tl(arg, 0); /* unimplemented */ rn =3D "'Diagnostic"; /* implementation dependent */ break; - case 23: + case CPO_REGISTER_23: switch (sel) { case 0: gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ @@ -7201,7 +7201,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 24: + case CPO_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -7213,7 +7213,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 25: + case CPO_REGISTER_25: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); @@ -7251,7 +7251,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 26: + case CPO_REGISTER_26: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); @@ -7261,7 +7261,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 27: + case CPO_REGISTER_27: switch (sel) { case 0: case 1: @@ -7274,7 +7274,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -7299,7 +7299,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 29: + case CPO_REGISTER_29: switch (sel) { case 0: case 2: @@ -7319,7 +7319,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 30: + case CPO_REGISTER_30: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); @@ -7330,7 +7330,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 31: + case CPO_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -7376,7 +7376,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) } =20 switch (reg) { - case 0: + case CPO_REGISTER_00: switch (sel) { case 0: gen_helper_mtc0_index(cpu_env, arg); @@ -7406,7 +7406,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 1: + case CPO_REGISTER_01: switch (sel) { case 0: /* ignored */ @@ -7453,7 +7453,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: gen_helper_mtc0_entrylo0(cpu_env, arg); @@ -7498,7 +7498,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: gen_helper_mtc0_entrylo1(cpu_env, arg); @@ -7513,7 +7513,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 4: + case CPO_REGISTER_04: switch (sel) { case 0: gen_helper_mtc0_context(cpu_env, arg); @@ -7533,7 +7533,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 5: + case CPO_REGISTER_05: switch (sel) { case 0: gen_helper_mtc0_pagemask(cpu_env, arg); @@ -7579,7 +7579,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 6: + case CPO_REGISTER_06: switch (sel) { case 0: gen_helper_mtc0_wired(cpu_env, arg); @@ -7619,7 +7619,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 7: + case CPO_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -7631,7 +7631,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 8: + case CPO_REGISTER_08: switch (sel) { case 0: /* ignored */ @@ -7653,7 +7653,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 9: + case CPO_REGISTER_09: switch (sel) { case 0: gen_helper_mtc0_count(cpu_env, arg); @@ -7664,7 +7664,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 10: + case CPO_REGISTER_10: switch (sel) { case 0: gen_helper_mtc0_entryhi(cpu_env, arg); @@ -7674,7 +7674,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 11: + case CPO_REGISTER_11: switch (sel) { case 0: gen_helper_mtc0_compare(cpu_env, arg); @@ -7685,7 +7685,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 12: + case CPO_REGISTER_12: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -7720,7 +7720,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 13: + case CPO_REGISTER_13: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -7736,7 +7736,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 14: + case CPO_REGISTER_14: switch (sel) { case 0: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -7746,7 +7746,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 15: + case CPO_REGISTER_15: switch (sel) { case 0: /* ignored */ @@ -7761,7 +7761,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 16: + case CPO_REGISTER_16: switch (sel) { case 0: gen_helper_mtc0_config0(cpu_env, arg); @@ -7810,7 +7810,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: gen_helper_mtc0_lladdr(cpu_env, arg); @@ -7830,7 +7830,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 18: + case CPO_REGISTER_18: switch (sel) { case 0: case 1: @@ -7848,7 +7848,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 19: + case CPO_REGISTER_19: switch (sel) { case 0: case 1: @@ -7866,7 +7866,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 20: + case CPO_REGISTER_20: switch (sel) { case 0: #if defined(TARGET_MIPS64) @@ -7879,7 +7879,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 21: + case CPO_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -7891,11 +7891,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; - case 22: + case CPO_REGISTER_22: /* ignored */ rn =3D "Diagnostic"; /* implementation dependent */ break; - case 23: + case CPO_REGISTER_23: switch (sel) { case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ @@ -7934,7 +7934,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 24: + case CPO_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -7945,7 +7945,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 25: + case CPO_REGISTER_25: switch (sel) { case 0: gen_helper_mtc0_performance0(cpu_env, arg); @@ -7983,7 +7983,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 26: + case CPO_REGISTER_26: switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); @@ -7994,7 +7994,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 27: + case CPO_REGISTER_27: switch (sel) { case 0: case 1: @@ -8007,7 +8007,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -8027,7 +8027,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 29: + case CPO_REGISTER_29: switch (sel) { case 0: case 2: @@ -8048,7 +8048,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 30: + case CPO_REGISTER_30: switch (sel) { case 0: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); @@ -8058,7 +8058,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; } break; - case 31: + case CPO_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -8108,7 +8108,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) check_insn(ctx, ISA_MIPS64); =20 switch (reg) { - case 0: + case CPO_REGISTER_00: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); @@ -8138,7 +8138,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 1: + case CPO_REGISTER_01: switch (sel) { case 0: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); @@ -8184,7 +8184,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 0)); @@ -8229,7 +8229,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 1)); @@ -8244,7 +8244,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 4: + case CPO_REGISTER_04: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context= )); @@ -8264,7 +8264,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 5: + case CPO_REGISTER_05: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); @@ -8309,7 +8309,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 6: + case CPO_REGISTER_06: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); @@ -8349,7 +8349,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 7: + case CPO_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -8360,7 +8360,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 8: + case CPO_REGISTER_08: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); @@ -8386,7 +8386,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 9: + case CPO_REGISTER_09: switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ @@ -8409,7 +8409,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 10: + case CPO_REGISTER_10: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); @@ -8419,7 +8419,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 11: + case CPO_REGISTER_11: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); @@ -8430,7 +8430,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 12: + case CPO_REGISTER_12: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); @@ -8455,7 +8455,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 13: + case CPO_REGISTER_13: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); @@ -8465,7 +8465,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 14: + case CPO_REGISTER_14: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -8475,7 +8475,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 15: + case CPO_REGISTER_15: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); @@ -8496,7 +8496,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 16: + case CPO_REGISTER_16: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); @@ -8535,7 +8535,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: gen_helper_dmfc0_lladdr(arg, cpu_env); @@ -8555,7 +8555,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 18: + case CPO_REGISTER_18: switch (sel) { case 0: case 1: @@ -8573,7 +8573,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 19: + case CPO_REGISTER_19: switch (sel) { case 0: case 1: @@ -8591,7 +8591,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 20: + case CPO_REGISTER_20: switch (sel) { case 0: check_insn(ctx, ISA_MIPS3); @@ -8602,7 +8602,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 21: + case CPO_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -8614,11 +8614,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) goto cp0_unimplemented; } break; - case 22: + case CPO_REGISTER_22: tcg_gen_movi_tl(arg, 0); /* unimplemented */ rn =3D "'Diagnostic"; /* implementation dependent */ break; - case 23: + case CPO_REGISTER_23: switch (sel) { case 0: gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ @@ -8644,7 +8644,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 24: + case CPO_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -8655,7 +8655,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 25: + case CPO_REGISTER_25: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); @@ -8693,7 +8693,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 26: + case CPO_REGISTER_26: switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); @@ -8703,7 +8703,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 27: + case CPO_REGISTER_27: switch (sel) { /* ignored */ case 0: @@ -8717,7 +8717,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -8737,7 +8737,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 29: + case CPO_REGISTER_29: switch (sel) { case 0: case 2: @@ -8757,7 +8757,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 30: + case CPO_REGISTER_30: switch (sel) { case 0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); @@ -8767,7 +8767,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 31: + case CPO_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -8812,7 +8812,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) } =20 switch (reg) { - case 0: + case CPO_REGISTER_00: switch (sel) { case 0: gen_helper_mtc0_index(cpu_env, arg); @@ -8842,7 +8842,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 1: + case CPO_REGISTER_01: switch (sel) { case 0: /* ignored */ @@ -8887,7 +8887,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 2: + case CPO_REGISTER_02: switch (sel) { case 0: gen_helper_dmtc0_entrylo0(cpu_env, arg); @@ -8932,7 +8932,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 3: + case CPO_REGISTER_03: switch (sel) { case 0: gen_helper_dmtc0_entrylo1(cpu_env, arg); @@ -8947,7 +8947,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 4: + case CPO_REGISTER_04: switch (sel) { case 0: gen_helper_mtc0_context(cpu_env, arg); @@ -8967,7 +8967,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 5: + case CPO_REGISTER_05: switch (sel) { case 0: gen_helper_mtc0_pagemask(cpu_env, arg); @@ -9012,7 +9012,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 6: + case CPO_REGISTER_06: switch (sel) { case 0: gen_helper_mtc0_wired(cpu_env, arg); @@ -9052,7 +9052,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 7: + case CPO_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -9064,7 +9064,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 8: + case CPO_REGISTER_08: switch (sel) { case 0: /* ignored */ @@ -9086,7 +9086,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 9: + case CPO_REGISTER_09: switch (sel) { case 0: gen_helper_mtc0_count(cpu_env, arg); @@ -9099,7 +9099,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 10: + case CPO_REGISTER_10: switch (sel) { case 0: gen_helper_mtc0_entryhi(cpu_env, arg); @@ -9109,7 +9109,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 11: + case CPO_REGISTER_11: switch (sel) { case 0: gen_helper_mtc0_compare(cpu_env, arg); @@ -9122,7 +9122,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 12: + case CPO_REGISTER_12: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -9157,7 +9157,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 13: + case CPO_REGISTER_13: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -9173,7 +9173,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 14: + case CPO_REGISTER_14: switch (sel) { case 0: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -9183,7 +9183,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 15: + case CPO_REGISTER_15: switch (sel) { case 0: /* ignored */ @@ -9198,7 +9198,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 16: + case CPO_REGISTER_16: switch (sel) { case 0: gen_helper_mtc0_config0(cpu_env, arg); @@ -9238,7 +9238,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 17: + case CPO_REGISTER_17: switch (sel) { case 0: gen_helper_mtc0_lladdr(cpu_env, arg); @@ -9258,7 +9258,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 18: + case CPO_REGISTER_18: switch (sel) { case 0: case 1: @@ -9276,7 +9276,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 19: + case CPO_REGISTER_19: switch (sel) { case 0: case 1: @@ -9294,7 +9294,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 20: + case CPO_REGISTER_20: switch (sel) { case 0: check_insn(ctx, ISA_MIPS3); @@ -9305,7 +9305,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 21: + case CPO_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -9317,11 +9317,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) goto cp0_unimplemented; } break; - case 22: + case CPO_REGISTER_22: /* ignored */ rn =3D "Diagnostic"; /* implementation dependent */ break; - case 23: + case CPO_REGISTER_23: switch (sel) { case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ @@ -9358,7 +9358,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 24: + case CPO_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -9369,7 +9369,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 25: + case CPO_REGISTER_25: switch (sel) { case 0: gen_helper_mtc0_performance0(cpu_env, arg); @@ -9407,7 +9407,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 26: + case CPO_REGISTER_26: switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); @@ -9418,7 +9418,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 27: + case CPO_REGISTER_27: switch (sel) { case 0: case 1: @@ -9431,7 +9431,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 28: + case CPO_REGISTER_28: switch (sel) { case 0: case 2: @@ -9451,7 +9451,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 29: + case CPO_REGISTER_29: switch (sel) { case 0: case 2: @@ -9472,7 +9472,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 30: + case CPO_REGISTER_30: switch (sel) { case 0: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); @@ -9482,7 +9482,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } break; - case 31: + case CPO_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533640952500.2566963112113; Thu, 3 Jan 2019 08:40:40 -0800 (PST) Received: from localhost ([127.0.0.1]:55910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf62x-0006FV-Po for importer@patchew.org; Thu, 03 Jan 2019 11:40:39 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5yL-0001gt-5H for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5yK-0008FY-9D for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:53 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:40850 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5yJ-00078B-Vh for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:52 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1367A1A2127; Thu, 3 Jan 2019 17:34:50 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id EE2FC1A2125; Thu, 3 Jan 2019 17:34:49 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:08 +0100 Message-Id: <1546533252-26601-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add fields for SAARI and SAAR CP0 registers. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/cpu.h | 10 ++++++++-- target/mips/machine.c | 6 ++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b095422..1c2c682 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t; * 3 BadInstrX * 4 GuestCtl1 GuestCtl0Ext * 5 GuestCtl2 - * 6 GuestCtl3 - * 7 + * 6 SAARI GuestCtl3 + * 7 SAAR * * * Register 12 Register 13 Register 14 Register 15 @@ -546,6 +546,12 @@ struct CPUMIPSState { * CP0 Register 9 */ int32_t CP0_Count; + uint32_t CP0_SAARI; +#define CP0SAARI_TARGET 0 /* 5..0 */ + uint64_t CP0_SAAR[2]; +#define CP0SAAR_BASE 12 /* 43..12 */ +#define CP0SAAR_SIZE 1 /* 5..1 */ +#define CP0SAAR_EN 0 /* * CP0 Register 10 */ diff --git a/target/mips/machine.c b/target/mips/machine.c index 704e9c0..111d7c3 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 15, - .minimum_version_id =3D 15, + .version_id =3D 16, + .minimum_version_id =3D 16, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), + VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533481309488.5280377595342; Thu, 3 Jan 2019 08:38:01 -0800 (PST) Received: from localhost ([127.0.0.1]:55888 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf60O-0003HP-2b for importer@patchew.org; Thu, 03 Jan 2019 11:38:00 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5y1-0001Jg-E3 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5xx-0007qA-W2 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:33 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:41592 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5xx-0007oO-Je for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:29 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E9BB01A211A; Thu, 3 Jan 2019 17:34:52 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id CA61B1A1529; Thu, 3 Jan 2019 17:34:52 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:09 +0100 Message-Id: <1546533252-26601-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 5/8] target/mips: Provide R/W access to SAARI and SAAR CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Provide R/W access to SAARI and SAAR CP0 registers. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/cpu.h | 1 + target/mips/helper.h | 6 +++++ target/mips/internal.h | 1 + target/mips/op_helper.c | 50 +++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= +--- 5 files changed, 120 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1c2c682..185702d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -901,6 +901,7 @@ struct CPUMIPSState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ + int saarp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/mips/helper.h b/target/mips/helper.h index c23e4e5..8872c46 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/internal.h b/target/mips/internal.h index 8b1b245..8f6fc91 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -61,6 +61,7 @@ struct mips_def_t { target_ulong CP0_EBaseWG_rw_bitmask; uint64_t insn_flags; enum mips_mmu_types mmu_type; + int32_t SAARP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index d1f1d1a..409c136 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return count; } =20 +target_ulong helper_mfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + +target_ulong helper_mfhc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; + } + return 0; +} + target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -1059,6 +1075,14 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env,= uint32_t sel) { return env->CP0_WatchLo[sel]; } + +target_ulong helper_dmfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1598,6 +1622,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulo= ng arg1) qemu_mutex_unlock_iothread(); } =20 +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D arg1 & 0x3f; + if (target <=3D 1) { + env->CP0_SAARI =3D target; + } +} + +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + } +} + +void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D + (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | + (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + } +} + void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/translate.c b/target/mips/translate.c index 6af292f..b0b926f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2501,6 +2501,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool saar; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -6498,6 +6499,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfhc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } + break; case CPO_REGISTER_17: switch (sel) { case 0: @@ -6568,6 +6580,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mthc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } case CPO_REGISTER_17: switch (sel) { case 0: @@ -6954,7 +6976,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -7659,7 +7690,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -8404,7 +8444,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_dmfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -9092,7 +9141,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533477486838.0003214894602; Thu, 3 Jan 2019 08:37:57 -0800 (PST) Received: from localhost ([127.0.0.1]:55884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf60F-00039S-8e for importer@patchew.org; Thu, 03 Jan 2019 11:37:51 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5y1-0001Ji-El for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5xx-0007pk-PE for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:33 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:41591 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5xx-0007oM-H8 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:29 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BA7761A2121; Thu, 3 Jan 2019 17:34:55 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A1F791A1529; Thu, 3 Jan 2019 17:34:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:10 +0100 Message-Id: <1546533252-26601-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add field and R/W access to ITU control register ICR0. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- hw/misc/mips_itu.c | 22 +++++++++++++++++++++- include/hw/misc/mips_itu.h | 4 ++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 43bbec4..4801958 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -55,9 +55,17 @@ typedef enum ITCView { ITCVIEW_EF_SYNC =3D 2, ITCVIEW_EF_TRY =3D 3, ITCVIEW_PV_SYNC =3D 4, - ITCVIEW_PV_TRY =3D 5 + ITCVIEW_PV_TRY =3D 5, + ITCVIEW_PV_ICR0 =3D 15, } ITCView; =20 +#define ITC_ICR0_CELL_NUM 16 +#define ITC_ICR0_BLK_GRAIN 8 +#define ITC_ICR0_BLK_GRAIN_MASK 0x7 +#define ITC_ICR0_ERR_AXI 2 +#define ITC_ICR0_ERR_PARITY 1 +#define ITC_ICR0_ERR_EXEC 0 + MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) { return &itu->tag_io; @@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr a= ddr, unsigned size) case ITCVIEW_PV_TRY: ret =3D view_pv_try_read(cell); break; + case ITCVIEW_PV_ICR0: + ret =3D s->icr0; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_read: Bad ITC View %d\n", (int)view); @@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, case ITCVIEW_PV_TRY: view_pv_try_write(cell); break; + case ITCVIEW_PV_ICR0: + if (data & 0x7) { + /* clear ERROR bits */ + s->icr0 &=3D ~(data & 0x7); + } + /* set BLK_GRAIN */ + s->icr0 &=3D ~0x700; + s->icr0 |=3D data & 0x700; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_write: Bad ITC View %d\n", (int)view); diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 030eb4a..45a0c51 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -66,6 +66,10 @@ typedef struct MIPSITUState { /* ITC Configuration Tags */ uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM]; MemoryRegion tag_io; + + /* ITU Control Register */ + uint64_t icr0; + } MIPSITUState; =20 /* Get ITC Configuration Tag memory region. */ --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533634707799.6080664930657; Thu, 3 Jan 2019 08:40:34 -0800 (PST) Received: from localhost ([127.0.0.1]:55905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf62r-00068p-H9 for importer@patchew.org; Thu, 03 Jan 2019 11:40:33 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5y1-0001Jj-Eo for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5xz-0007sV-F1 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:33 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:41615 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5xz-0007qF-31 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:31 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 03D7A1A2122; Thu, 3 Jan 2019 17:34:58 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DAA261A1529; Thu, 3 Jan 2019 17:34:57 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:11 +0100 Message-Id: <1546533252-26601-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 7/8] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update ITU to utilize SAARI and SAAR CP0 registers. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- hw/mips/cps.c | 8 ++++++++ hw/misc/mips_itu.c | 28 ++++++++++++++++++++++------ include/hw/misc/mips_itu.h | 4 ++++ target/mips/cpu.h | 5 +++++ target/mips/op_helper.c | 14 ++++++++++++++ 5 files changed, 53 insertions(+), 6 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4285d19..fc97f59 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) Error *err =3D NULL; target_ulong gcr_base; bool itu_present =3D false; + bool saar_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { cpu =3D MIPS_CPU(cpu_create(s->cpu_type)); @@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) itu_present =3D true; /* Attach ITC Tag to the VP */ env->itc_tag =3D mips_itu_get_tag_region(&s->itu); + env->itu =3D &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } =20 cpu =3D MIPS_CPU(first_cpu); env =3D &cpu->env; + saar_present =3D (bool)env->saarp; =20 /* Inter-Thread Communication Unit */ if (itu_present) { @@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **e= rrp) =20 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &er= r); + object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", + &err); + if (saar_present) { + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_S= AAR); + } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 4801958..5c49bdd 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -84,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, u= nsigned size) return tag->ITCAddressMap[index]; } =20 -static void itc_reconfigure(MIPSITUState *tag) +void itc_reconfigure(MIPSITUState *tag) { uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 + if (tag->saar_present) { + address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; + size =3D 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f); + is_enabled =3D *(uint64_t *) tag->saar & 1; + } + memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -150,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + if (s->saar_present) { + return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & + ITC_ICR0_BLK_GRAIN_MASK); + } else { + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + } } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -499,10 +510,15 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D - ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | - (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + if (s->saar_present) { + *(uint64_t *) s->saar =3D 0x11 << 1; + s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; + } else { + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D + ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | + (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + } itc_reconfigure(s); =20 itc_reset_cells(s); diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 45a0c51..c44e767 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,6 +70,10 @@ typedef struct MIPSITUState { /* ITU Control Register */ uint64_t icr0; =20 + /* SAAR */ + bool saar_present; + void *saar; + } MIPSITUState; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 185702d..48e86d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -326,6 +326,7 @@ struct TCState { =20 }; =20 +struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; @@ -917,6 +918,7 @@ struct CPUMIPSState { const mips_def_t *cpu_model; void *irq[8]; QEMUTimer *timer; /* Internal timer */ + struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ }; @@ -1059,6 +1061,9 @@ void cpu_set_exception_base(int vp_index, target_ulon= g address); /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); =20 +/* mips_itu.c */ +void itc_reconfigure(struct MIPSITUState *tag); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 409c136..aebad24 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1635,6 +1635,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) uint32_t target =3D env->CP0_SAARI & 0x3f; if (target < 2) { env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 @@ -1645,6 +1652,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) env->CP0_SAAR[target] =3D (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 --=20 2.7.4 From nobody Mon May 6 05:50:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546533478857318.14789593074465; Thu, 3 Jan 2019 08:37:58 -0800 (PST) Received: from localhost ([127.0.0.1]:55882 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf60D-00038y-8n for importer@patchew.org; Thu, 03 Jan 2019 11:37:49 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55920) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gf5y1-0001Jf-Dw for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gf5xz-0007sI-B3 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:33 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:41614 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gf5xz-0007qE-33 for qemu-devel@nongnu.org; Thu, 03 Jan 2019 11:35:31 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 150E31A2125; Thu, 3 Jan 2019 17:35:00 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id F06561A1529; Thu, 3 Jan 2019 17:34:59 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 3 Jan 2019 17:34:12 +0100 Message-Id: <1546533252-26601-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update ITU to handle bus errors. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- hw/misc/mips_itu.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 5c49bdd..e8860dc 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c) view_pv_common_write(c); } =20 +static void raise_exception(int excp) +{ + current_cpu->exception_index =3D excp; + cpu_loop_exit(current_cpu); +} + static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) { MIPSITUState *s =3D (MIPSITUState *)opaque; @@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr = addr, unsigned size) ITCView view =3D get_itc_view(addr); uint64_t ret =3D -1; =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return 0; + } + switch (view) { case ITCVIEW_BYPASS: ret =3D view_bypass_read(cell); @@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, ITCStorageCell *cell =3D get_cell(s, addr); ITCView view =3D get_itc_view(addr); =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return; + } + switch (view) { case ITCVIEW_BYPASS: view_bypass_write(cell, data); --=20 2.7.4