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Thu, 06 Dec 2018 06:04:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUrSO-0000Jw-Nn for qemu-devel@nongnu.org; Thu, 06 Dec 2018 06:04:42 -0500 Received: from out1.zte.com.cn ([202.103.147.172]:41282 helo=mxct.zte.com.cn) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUrSF-00008r-EI; Thu, 06 Dec 2018 06:04:27 -0500 Received: from mse01.zte.com.cn (unknown [10.30.3.20]) by Forcepoint Email with ESMTPS id 49F1B9EA645449850BCA; Thu, 6 Dec 2018 19:04:13 +0800 (CST) Received: from notes_smtp.zte.com.cn ([10.30.1.239]) by mse01.zte.com.cn with ESMTP id wB6B3x9L072804; Thu, 6 Dec 2018 19:03:59 +0800 (GMT-8) (envelope-from peng.hao2@zte.com.cn) Received: from localhost.localdomain.localdomain ([10.74.120.59]) by szsmtp06.zte.com.cn (Lotus Domino Release 8.5.3FP6) with ESMTP id 2018120619043131-15124399 ; Thu, 6 Dec 2018 19:04:31 +0800 From: Peng Hao To: peter.maydell@linaro.org, drjones@redhat.com, philmd@redhat.com Date: Thu, 6 Dec 2018 19:25:58 +0800 Message-Id: <1544095560-70807-4-git-send-email-peng.hao2@zte.com.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1544095560-70807-1-git-send-email-peng.hao2@zte.com.cn> References: <1544095560-70807-1-git-send-email-peng.hao2@zte.com.cn> X-MIMETrack: Itemize by SMTP Server on SZSMTP06/server/zte_ltd(Release 8.5.3FP6|November 21, 2013) at 2018-12-06 19:04:31, Serialize by Router on notes_smtp/zte_ltd(Release 9.0.1FP7|August 17, 2016) at 2018-12-06 19:03:48, Serialize complete at 2018-12-06 19:03:48 X-MAIL: mse01.zte.com.cn wB6B3x9L072804 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 202.103.147.172 Subject: [Qemu-devel] [PATCH V12 3/5] hw/misc/pvpanic: Add the PCI interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peng Hao , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add pvpanic new type "TYPE_PVPANIC_PCI" Signed-off-by: Peng Hao --- hw/misc/pvpanic.c | 62 +++++++++++++++++++++++++++++++++++++++++++= +--- include/hw/misc/pvpanic.h | 1 + include/hw/pci/pci.h | 1 + 3 files changed, 60 insertions(+), 4 deletions(-) diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c index 0f23a67..9fb9168 100644 --- a/hw/misc/pvpanic.c +++ b/hw/misc/pvpanic.c @@ -2,10 +2,12 @@ * QEMU simulated pvpanic device. * * Copyright Fujitsu, Corp. 2013 + * Copyright (c) 2018 ZTE Ltd. * * Authors: * Wen Congyang * Hu Tao + * Peng Hao * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -18,6 +20,7 @@ =20 #include "hw/nvram/fw_cfg.h" #include "hw/misc/pvpanic.h" +#include "hw/pci/pci.h" =20 /* The bit of supported pv event */ #define PVPANIC_F_PANICKED 0 @@ -27,6 +30,8 @@ =20 #define PVPANIC_ISA_DEVICE(obj) \ OBJECT_CHECK(PVPanicISAState, (obj), TYPE_PVPANIC) +#define PVPANIC_PCI_DEVICE(obj) \ + OBJECT_CHECK(PVPanicPCIState, (obj), TYPE_PVPANIC_PCI) =20 static void handle_event(int event) { @@ -56,21 +61,31 @@ typedef struct PVPanicISAState { MemoryRegion mr; } PVPanicISAState; =20 +/* PVPanicPCIState for PCI device and + * use mmio. + */ +typedef struct PVPanicPCIState { + /*< private>*/ + PCIDevice dev; + + /**/ + MemoryRegion mr; +} PVPanicPCIState; /* return supported events on read */ -static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned si= ze) +static uint64_t pvpanic_read(void *opaque, hwaddr addr, unsigned size) { return PVPANIC_PANICKED; } =20 -static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val, +static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { handle_event(val); } =20 static const MemoryRegionOps pvpanic_ops =3D { - .read =3D pvpanic_ioport_read, - .write =3D pvpanic_ioport_write, + .read =3D pvpanic_read, + .write =3D pvpanic_write, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -125,9 +140,48 @@ static TypeInfo pvpanic_isa_info =3D { .class_init =3D pvpanic_isa_class_init, }; =20 +/* pvpanic pci device*/ + +static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp) +{ + PVPanicPCIState *s =3D DO_UPCAST(PVPanicPCIState, dev, dev); + + memory_region_init_io(&s->mr, OBJECT(s), &pvpanic_ops, s, + TYPE_PVPANIC_PCI, 2); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mr); +} + +static void pvpanic_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(klass); + + pc->realize =3D pvpanic_pci_realizefn; + pc->vendor_id =3D PCI_VENDOR_ID_REDHAT; + pc->device_id =3D PCI_DEVICE_ID_REDHAT_PVPANIC; + pc->revision =3D 1; + pc->class_id =3D PCI_CLASS_SYSTEM_OTHER; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); +} + +static TypeInfo pvpanic_pci_info =3D { + .name =3D TYPE_PVPANIC_PCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PVPanicPCIState), + .class_init =3D pvpanic_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { } + } +}; + + static void pvpanic_register_types(void) { type_register_static(&pvpanic_isa_info); + type_register_static(&pvpanic_pci_info); } =20 type_init(pvpanic_register_types) diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h index 1ee071a..477cc36 100644 --- a/include/hw/misc/pvpanic.h +++ b/include/hw/misc/pvpanic.h @@ -15,6 +15,7 @@ #define HW_MISC_PVPANIC_H =20 #define TYPE_PVPANIC "pvpanic" +#define TYPE_PVPANIC_PCI "pvpanic-pci" =20 #define PVPANIC_IOPORT_PROP "ioport" =20 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e6514bb..92622f7 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -103,6 +103,7 @@ extern bool pci_available; #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 +#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0101 =20 #define FMT_PCIBUS PRIx64 =20 --=20 1.8.3.1