From nobody Fri Apr 19 22:40:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544003075390270.16220026075587; Wed, 5 Dec 2018 01:44:35 -0800 (PST) Received: from localhost ([::1]:33088 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUTjJ-0002v1-An for importer@patchew.org; Wed, 05 Dec 2018 04:44:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50278) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUTi9-0001y2-RC for qemu-devel@nongnu.org; Wed, 05 Dec 2018 04:43:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUTi5-00036B-CT for qemu-devel@nongnu.org; Wed, 05 Dec 2018 04:43:17 -0500 Received: from mx01.hxt-semitech.com ([223.203.96.7]:56579 helo=barracuda.hxt-semitech.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUTi4-0002kv-Fu for qemu-devel@nongnu.org; Wed, 05 Dec 2018 04:43:13 -0500 Received: from HXTBJIDCEMVIW02.hxtcorp.net ([10.128.0.15]) by barracuda.hxt-semitech.com with ESMTP id ghXhESU4Ck96YH6g (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NO); Wed, 05 Dec 2018 17:42:58 +0800 (CST) Received: from localhost.localdomain (10.64.0.74) by HXTBJIDCEMVIW02.hxtcorp.net (10.128.0.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 5 Dec 2018 17:42:09 +0800 X-ASG-Debug-ID: 1544002978-093b7e45f7009e0001-jgbH7p X-Barracuda-Envelope-From: huan.xiong@hxt-semitech.com From: Huan Xiong To: Date: Wed, 5 Dec 2018 17:41:26 +0800 X-ASG-Orig-Subj: [PATCH] hw/pci-bridge: check invalid slot number for root and downstream port Message-ID: <1544002886-11333-1-git-send-email-huan.xiong@hxt-semitech.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.64.0.74] X-ClientProxiedBy: HXTBJIDCEMVIW02.hxtcorp.net (10.128.0.15) To HXTBJIDCEMVIW02.hxtcorp.net (10.128.0.15) X-Barracuda-Connect: UNKNOWN[10.128.0.15] X-Barracuda-Start-Time: 1544002978 X-Barracuda-Encrypted: ECDHE-RSA-AES256-SHA384 X-Barracuda-URL: https://192.168.50.101:443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at hxt-semitech.com X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: SPAM GLOBAL 0.9920 1.0000 4.2503 X-Barracuda-Spam-Score: 4.25 X-Barracuda-Spam-Status: No, SCORE=4.25 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.63098 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 223.203.96.7 Subject: [Qemu-devel] [PATCH] hw/pci-bridge: check invalid slot number for root and downstream port X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since root and downstream port have only one slot, device should be connected to them using slot 0. QEMU doesn't have a check for that and starts up when a non-zero slot is specified, though the device is not seen in guest OS. The change fixes that by adding a check in PCI device "attr" property setter function. The check is performed only if a PCI device has been connected to a bus, otherwise it does nothing. The latter occurs because setter function is also called in object instantiation phase to set property default value. Signed-off-by: Huan Xiong --- hw/core/qdev-properties.c | 5 ++++- hw/pci-bridge/pcie_root_port.c | 2 +- hw/pci-bridge/xio3130_downstream.c | 2 +- hw/pci/pci.c | 13 +++++++++++++ include/hw/pci/pci.h | 1 + 5 files changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 35072de..6e79219 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -654,6 +654,8 @@ static void set_pci_devfn(Object *obj, Visitor *v, cons= t char *name, void *opaque, Error **errp) { DeviceState *dev =3D DEVICE(obj); + BusState *bus =3D qdev_get_parent_bus(dev); + BusClass *bus_class =3D bus ? BUS_GET_CLASS(bus) : NULL; Property *prop =3D opaque; int32_t value, *ptr =3D qdev_get_prop_ptr(dev, prop); unsigned int slot, fn, n; @@ -687,7 +689,8 @@ static void set_pci_devfn(Object *obj, Visitor *v, cons= t char *name, goto invalid; } } - if (str[n] !=3D '\0' || fn > 7 || slot > 31) { + if (str[n] !=3D '\0' || fn > 7 || slot > 31 || (bus_class && + bus_class->max_dev !=3D 0 && slot >=3D bus_class->max_dev)) { goto invalid; } *ptr =3D slot << 3 | fn; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8c..ee42411 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -61,7 +61,7 @@ static void rp_realize(PCIDevice *d, Error **errp) int rc; =20 pci_config_set_interrupt_pin(d->config, 1); - pci_bridge_initfn(d, TYPE_PCIE_BUS); + pci_bridge_initfn(d, TYPE_PCIE_DOWNSTREAM_BUS); pcie_port_init_reg(d); =20 rc =3D pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 467bbab..960a90c 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -62,7 +62,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Erro= r **errp) PCIESlot *s =3D PCIE_SLOT(d); int rc; =20 - pci_bridge_initfn(d, TYPE_PCIE_BUS); + pci_bridge_initfn(d, TYPE_PCIE_DOWNSTREAM_BUS); pcie_port_init_reg(d); =20 rc =3D msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 56b13b3..457736d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -187,6 +187,18 @@ static const TypeInfo pcie_bus_info =3D { .parent =3D TYPE_PCI_BUS, }; =20 +static void pcie_downstream_bus_class_init(ObjectClass *klass, void *data) +{ + BusClass *k =3D BUS_CLASS(klass); + k->max_dev =3D 1; +} + +static const TypeInfo pcie_downstream_bus_info =3D { + .name =3D TYPE_PCIE_DOWNSTREAM_BUS, + .parent =3D TYPE_PCIE_BUS, + .class_init =3D pcie_downstream_bus_class_init, +}; + static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); static void pci_update_mappings(PCIDevice *d); static void pci_irq_handler(void *opaque, int irq_num, int level); @@ -2681,6 +2693,7 @@ static void pci_register_types(void) { type_register_static(&pci_bus_info); type_register_static(&pcie_bus_info); + type_register_static(&pcie_downstream_bus_info); type_register_static(&conventional_pci_interface_info); type_register_static(&pcie_interface_info); type_register_static(&pci_device_type_info); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e6514bb..2253757 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -393,6 +393,7 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, = int pin); #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE= _PCI_BUS) #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_P= CI_BUS) #define TYPE_PCIE_BUS "PCIE" +#define TYPE_PCIE_DOWNSTREAM_BUS "PCIE-downstream" =20 bool pci_bus_is_express(PCIBus *bus); bool pci_bus_is_root(PCIBus *bus); --=20 2.7.4