From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543941880195831.492176729495; Tue, 4 Dec 2018 08:44:40 -0800 (PST) Received: from localhost ([::1]:57840 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDoN-00029z-2f for importer@patchew.org; Tue, 04 Dec 2018 11:44:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjD-0002ZB-H2 for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDWR-0005Bb-MX for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:08 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36286) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDWR-0005BG-FB for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:07 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 869FD2BEF1; Tue, 4 Dec 2018 16:26:06 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 15C315C237; Tue, 4 Dec 2018 16:26:06 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:05 -0700 Message-ID: <154394076572.28192.17922483382108051842.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 04 Dec 2018 16:26:06 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 1/9] pcie: Create enums for link speed and width X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" In preparation for reporting higher virtual link speeds and widths, create enums and macros to help us manage them. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci/pcie.c | 7 ++++--- hw/vfio/pci.c | 3 ++- include/hw/pci/pcie_regs.h | 23 +++++++++++++++++++++-- 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 6c91bd44a0a5..914a5261a79b 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -68,11 +68,12 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t = type, uint8_t version) pci_set_long(exp_cap + PCI_EXP_LNKCAP, (port << PCI_EXP_LNKCAP_PN_SHIFT) | PCI_EXP_LNKCAP_ASPMS_0S | - PCI_EXP_LNK_MLW_1 | - PCI_EXP_LNK_LS_25); + QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | + QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); =20 pci_set_word(exp_cap + PCI_EXP_LNKSTA, - PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); + QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | + QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); =20 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5c7bd9698496..74f9a46b4be0 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1897,7 +1897,8 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, i= nt pos, uint8_t size, PCI_EXP_TYPE_ENDPOINT << 4, PCI_EXP_FLAGS_TYPE); vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, - PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, = ~0); + QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | + QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)= , ~0); vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); } =20 diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index a95522a13b04..ad4e7808b8ac 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -34,10 +34,29 @@ =20 /* PCI_EXP_LINK{CAP, STA} */ /* link speed */ -#define PCI_EXP_LNK_LS_25 1 +typedef enum PCIExpLinkSpeed { + QEMU_PCI_EXP_LNK_2_5GT =3D 1, + QEMU_PCI_EXP_LNK_5GT, + QEMU_PCI_EXP_LNK_8GT, + QEMU_PCI_EXP_LNK_16GT, +} PCIExpLinkSpeed; + +#define QEMU_PCI_EXP_LNKCAP_MLS(speed) (speed) +#define QEMU_PCI_EXP_LNKSTA_CLS QEMU_PCI_EXP_LNKCAP_MLS + +typedef enum PCIExpLinkWidth { + QEMU_PCI_EXP_LNK_X1 =3D 1, + QEMU_PCI_EXP_LNK_X2 =3D 2, + QEMU_PCI_EXP_LNK_X4 =3D 4, + QEMU_PCI_EXP_LNK_X8 =3D 8, + QEMU_PCI_EXP_LNK_X12 =3D 12, + QEMU_PCI_EXP_LNK_X16 =3D 16, + QEMU_PCI_EXP_LNK_X32 =3D 32, +} PCIExpLinkWidth; =20 #define PCI_EXP_LNK_MLW_SHIFT ctz32(PCI_EXP_LNKCAP_MLW) -#define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT) +#define QEMU_PCI_EXP_LNKCAP_MLW(width) (width << PCI_EXP_LNK_MLW_SHIFT) +#define QEMU_PCI_EXP_LNKSTA_NLW QEMU_PCI_EXP_LNKCAP_MLW =20 /* PCI_EXP_LINKCAP */ #define PCI_EXP_LNKCAP_ASPMS_SHIFT ctz32(PCI_EXP_LNKCAP_ASPMS) From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543941693895567.3329516806903; Tue, 4 Dec 2018 08:41:33 -0800 (PST) Received: from localhost ([::1]:57818 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDlM-0006yD-Kk for importer@patchew.org; Tue, 04 Dec 2018 11:41:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjD-0002iF-8U for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDWX-0005J2-Gt for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:16 -0500 Received: from mx1.redhat.com ([209.132.183.28]:29569) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDWX-0005IG-9H for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:13 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8007483F40; Tue, 4 Dec 2018 16:26:12 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id E0AA67F1A7; Tue, 4 Dec 2018 16:26:11 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:11 -0700 Message-ID: <154394077152.28192.11886427713872503309.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 04 Dec 2018 16:26:12 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 2/9] pci: Sync PCIe downstream port LNKSTA on read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The PCIe link speed and width between a downstream device and its upstream port is negotiated on real hardware and susceptible to dynamic changes due to signal issues and power management. In the emulated device case there is no real hardware link, but we still might wish to have some consistency between endpoint and downstream port via a virtual negotiation. There is of course a real link for assigned devices and this same virtual negotiation allows the downstream port to match the endpoint, synchronizing on every read to support underlying physical hardware dynamically adjusting the link. This negotiation is intentionally unidirectional for compatibility. If the endpoint exceeds the capabilities of the downstream port or there is no endpoint device, the downstream port reports negotiation to its maximum speed and width, matching the previous case where negotiation was absent. De-tuning the endpoint to match a virtual link doesn't seem to benefit anyone and is a condition we've thus far reported without functional issues. Note that PCI_EXP_LNKSTA is already ignored for migration compatibility via pcie_cap_v1_fill(). Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/pci/pci.c | 4 ++++ hw/pci/pcie.c | 39 +++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 13 +++++++++++++ include/hw/pci/pcie.h | 1 + 4 files changed, 57 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 56b13b3320ec..495db3b9e18a 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1353,6 +1353,10 @@ uint32_t pci_default_read_config(PCIDevice *d, { uint32_t val =3D 0; =20 + if (pci_is_express_downstream_port(d) && + ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { + pcie_sync_bridge_lnk(d); + } memcpy(&val, d->config + address, len); return le32_to_cpu(val); } diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 914a5261a79b..61b7b96c52cd 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -729,6 +729,45 @@ void pcie_add_capability(PCIDevice *dev, memset(dev->cmask + offset, 0xFF, size); } =20 +/* + * Sync the PCIe Link Status negotiated speed and width of a bridge with t= he + * downstream device. If downstream device is not present, re-write with = the + * Link Capability fields. Limit width and speed to bridge capabilities f= or + * compatibility. Use config_read to access the downstream device since it + * could be an assigned device with volatile link information. + */ +void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) +{ + PCIBridge *br =3D PCI_BRIDGE(bridge_dev); + PCIBus *bus =3D pci_bridge_get_sec_bus(br); + PCIDevice *target =3D bus->devices[0]; + uint8_t *exp_cap =3D bridge_dev->config + bridge_dev->exp.exp_cap; + uint16_t lnksta, lnkcap =3D pci_get_word(exp_cap + PCI_EXP_LNKCAP); + + if (!target || !target->exp.exp_cap) { + lnksta =3D lnkcap; + } else { + lnksta =3D target->config_read(target, + target->exp.exp_cap + PCI_EXP_LNKSTA, + sizeof(lnksta)); + + if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW))= { + lnksta &=3D ~PCI_EXP_LNKSTA_NLW; + lnksta |=3D lnkcap & PCI_EXP_LNKCAP_MLW; + } + + if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS))= { + lnksta &=3D ~PCI_EXP_LNKSTA_CLS; + lnksta |=3D lnkcap & PCI_EXP_LNKCAP_SLS; + } + } + + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, + PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & + (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); +} + /************************************************************************** * pci express extended capability helper functions */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e6514bba23aa..eb12fa112ed2 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -737,6 +737,19 @@ static inline int pci_is_express(const PCIDevice *d) return d->cap_present & QEMU_PCI_CAP_EXPRESS; } =20 +static inline int pci_is_express_downstream_port(const PCIDevice *d) +{ + uint8_t type; + + if (!pci_is_express(d) || !d->exp.exp_cap) { + return 0; + } + + type =3D pcie_cap_get_type(d); + + return type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || type =3D=3D PCI_EXP_TYPE= _ROOT_PORT; +} + static inline uint32_t pci_config_size(const PCIDevice *d) { return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_S= IZE; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b71e36970345..1976909ab4c8 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -126,6 +126,7 @@ uint16_t pcie_find_capability(PCIDevice *dev, uint16_t = cap_id); void pcie_add_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, uint16_t offset, uint16_t size); +void pcie_sync_bridge_lnk(PCIDevice *dev); =20 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154394232786869.69557231526494; Tue, 4 Dec 2018 08:52:07 -0800 (PST) Received: from localhost ([::1]:57892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDvZ-0001M3-Qa for importer@patchew.org; Tue, 04 Dec 2018 11:52:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjC-0002lL-JN for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDWd-0005No-H5 for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:20 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53046) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDWd-0005NT-9b for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:19 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4F8B71555A; Tue, 4 Dec 2018 16:26:18 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id D76075DD8A; Tue, 4 Dec 2018 16:26:17 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:17 -0700 Message-ID: <154394077749.28192.1229512133780284321.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 04 Dec 2018 16:26:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 3/9] qapi: Define PCIe link speed and width properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Create properties to be able to define speeds and widths for PCIe links. The only tricky bit here is that our get and set callbacks translate from the fixed QAPI automagic enums to those we define in PCI code to represent the actual register segment value. Cc: Eric Blake Cc: Markus Armbruster Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Markus Armbruster --- hw/core/qdev-properties.c | 178 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/qdev-properties.h | 8 ++ qapi/common.json | 42 ++++++++++ 3 files changed, 228 insertions(+) diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 35072dec1ecf..f5ca5b821a79 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -1327,3 +1327,181 @@ const PropertyInfo qdev_prop_off_auto_pcibar =3D { .set =3D set_enum, .set_default_value =3D set_default_value_enum, }; + +/* --- PCIELinkSpeed 2_5/5/8/16 -- */ + +static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + DeviceState *dev =3D DEVICE(obj); + Property *prop =3D opaque; + PCIExpLinkSpeed *p =3D qdev_get_prop_ptr(dev, prop); + PCIELinkSpeed speed; + + switch (*p) { + case QEMU_PCI_EXP_LNK_2_5GT: + speed =3D PCIE_LINK_SPEED_2_5; + break; + case QEMU_PCI_EXP_LNK_5GT: + speed =3D PCIE_LINK_SPEED_5; + break; + case QEMU_PCI_EXP_LNK_8GT: + speed =3D PCIE_LINK_SPEED_8; + break; + case QEMU_PCI_EXP_LNK_16GT: + speed =3D PCIE_LINK_SPEED_16; + break; + default: + /* Unreachable */ + abort(); + } + + visit_type_enum(v, prop->name, (int *)&speed, prop->info->enum_table, = errp); +} + +static void set_prop_pcielinkspeed(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + DeviceState *dev =3D DEVICE(obj); + Property *prop =3D opaque; + PCIExpLinkSpeed *p =3D qdev_get_prop_ptr(dev, prop); + PCIELinkSpeed speed; + Error *local_err =3D NULL; + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_enum(v, prop->name, (int *)&speed, + prop->info->enum_table, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + switch (speed) { + case PCIE_LINK_SPEED_2_5: + *p =3D QEMU_PCI_EXP_LNK_2_5GT; + break; + case PCIE_LINK_SPEED_5: + *p =3D QEMU_PCI_EXP_LNK_5GT; + break; + case PCIE_LINK_SPEED_8: + *p =3D QEMU_PCI_EXP_LNK_8GT; + break; + case PCIE_LINK_SPEED_16: + *p =3D QEMU_PCI_EXP_LNK_16GT; + break; + default: + /* Unreachable */ + abort(); + } +} + +const PropertyInfo qdev_prop_pcie_link_speed =3D { + .name =3D "PCIELinkSpeed", + .description =3D "2_5/5/8/16", + .enum_table =3D &PCIELinkSpeed_lookup, + .get =3D get_prop_pcielinkspeed, + .set =3D set_prop_pcielinkspeed, + .set_default_value =3D set_default_value_enum, +}; + +/* --- PCIELinkWidth 1/2/4/8/12/16/32 -- */ + +static void get_prop_pcielinkwidth(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + DeviceState *dev =3D DEVICE(obj); + Property *prop =3D opaque; + PCIExpLinkWidth *p =3D qdev_get_prop_ptr(dev, prop); + PCIELinkWidth width; + + switch (*p) { + case QEMU_PCI_EXP_LNK_X1: + width =3D PCIE_LINK_WIDTH_1; + break; + case QEMU_PCI_EXP_LNK_X2: + width =3D PCIE_LINK_WIDTH_2; + break; + case QEMU_PCI_EXP_LNK_X4: + width =3D PCIE_LINK_WIDTH_4; + break; + case QEMU_PCI_EXP_LNK_X8: + width =3D PCIE_LINK_WIDTH_8; + break; + case QEMU_PCI_EXP_LNK_X12: + width =3D PCIE_LINK_WIDTH_12; + break; + case QEMU_PCI_EXP_LNK_X16: + width =3D PCIE_LINK_WIDTH_16; + break; + case QEMU_PCI_EXP_LNK_X32: + width =3D PCIE_LINK_WIDTH_32; + break; + default: + /* Unreachable */ + abort(); + } + + visit_type_enum(v, prop->name, (int *)&width, prop->info->enum_table, = errp); +} + +static void set_prop_pcielinkwidth(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + DeviceState *dev =3D DEVICE(obj); + Property *prop =3D opaque; + PCIExpLinkWidth *p =3D qdev_get_prop_ptr(dev, prop); + PCIELinkWidth width; + Error *local_err =3D NULL; + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_enum(v, prop->name, (int *)&width, + prop->info->enum_table, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + switch (width) { + case PCIE_LINK_WIDTH_1: + *p =3D QEMU_PCI_EXP_LNK_X1; + break; + case PCIE_LINK_WIDTH_2: + *p =3D QEMU_PCI_EXP_LNK_X2; + break; + case PCIE_LINK_WIDTH_4: + *p =3D QEMU_PCI_EXP_LNK_X4; + break; + case PCIE_LINK_WIDTH_8: + *p =3D QEMU_PCI_EXP_LNK_X8; + break; + case PCIE_LINK_WIDTH_12: + *p =3D QEMU_PCI_EXP_LNK_X12; + break; + case PCIE_LINK_WIDTH_16: + *p =3D QEMU_PCI_EXP_LNK_X16; + break; + case PCIE_LINK_WIDTH_32: + *p =3D QEMU_PCI_EXP_LNK_X32; + break; + default: + /* Unreachable */ + abort(); + } +} + +const PropertyInfo qdev_prop_pcie_link_width =3D { + .name =3D "PCIELinkWidth", + .description =3D "1/2/4/8/12/16/32", + .enum_table =3D &PCIELinkWidth_lookup, + .get =3D get_prop_pcielinkwidth, + .set =3D set_prop_pcielinkwidth, + .set_default_value =3D set_default_value_enum, +}; diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 4f60cc88f325..6a13a284c48c 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -36,6 +36,8 @@ extern const PropertyInfo qdev_prop_uuid; extern const PropertyInfo qdev_prop_arraylen; extern const PropertyInfo qdev_prop_link; extern const PropertyInfo qdev_prop_off_auto_pcibar; +extern const PropertyInfo qdev_prop_pcie_link_speed; +extern const PropertyInfo qdev_prop_pcie_link_width; =20 #define DEFINE_PROP(_name, _state, _field, _prop, _type) { \ .name =3D (_name), \ @@ -217,6 +219,12 @@ extern const PropertyInfo qdev_prop_off_auto_pcibar; #define DEFINE_PROP_OFF_AUTO_PCIBAR(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_off_auto_pcibar, \ OffAutoPCIBAR) +#define DEFINE_PROP_PCIE_LINK_SPEED(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_speed, \ + PCIExpLinkSpeed) +#define DEFINE_PROP_PCIE_LINK_WIDTH(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_width, \ + PCIExpLinkWidth) =20 #define DEFINE_PROP_UUID(_name, _state, _field) { \ .name =3D (_name), \ diff --git a/qapi/common.json b/qapi/common.json index 021174f04ea4..b6f3cca35c7e 100644 --- a/qapi/common.json +++ b/qapi/common.json @@ -127,6 +127,48 @@ { 'enum': 'OffAutoPCIBAR', 'data': [ 'off', 'auto', 'bar0', 'bar1', 'bar2', 'bar3', 'bar4', 'bar5' = ] } =20 +## +# @PCIELinkSpeed: +# +# An enumeration of PCIe link speeds in units of GT/s +# +# @2_5: 2.5GT/s +# +# @5: 5.0GT/s +# +# @8: 8.0GT/s +# +# @16: 16.0GT/s +# +# Since: 3.2 +## +{ 'enum': 'PCIELinkSpeed', + 'data': [ '2_5', '5', '8', '16' ] } + +## +# @PCIELinkWidth: +# +# An enumeration of PCIe link width +# +# @1: x1 +# +# @2: x2 +# +# @4: x4 +# +# @8: x8 +# +# @12: x12 +# +# @16: x16 +# +# @32: x32 +# +# Since: 3.2 +## +{ 'enum': 'PCIELinkWidth', + 'data': [ '1', '2', '4', '8', '12', '16', '32' ] } + ## # @SysEmuTarget: # From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543941667657563.040795552108; Tue, 4 Dec 2018 08:41:07 -0800 (PST) Received: from localhost ([::1]:57815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDkg-0006Ok-K6 for importer@patchew.org; Tue, 04 Dec 2018 11:40:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDij-0002ZB-3w for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:38:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDWo-0005Ww-FR for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:33 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53134) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDWo-0005WT-98 for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:30 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 642CC13A9B; Tue, 4 Dec 2018 16:26:29 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id B6BD77EFF4; Tue, 4 Dec 2018 16:26:23 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:23 -0700 Message-ID: <154394078336.28192.11850479111762649553.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 04 Dec 2018 16:26:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 4/9] pcie: Add link speed and width fields to PCIESlot X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Add fields allowing the PCIe link speed and width of a PCIESlot to be configured, with an instance_post_init callback on the root port parent class to set defaults. This allows child classes to set these via properties or via their own instance_init callback, without requiring all implementions to support arbitrary user selected values. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/pci-bridge/pcie_root_port.c | 14 ++++++++++++++ include/hw/pci/pcie_port.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8cd4a36..34ad76743c44 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -140,6 +140,19 @@ static Property rp_props[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +static void rp_instance_post_init(Object *obj) +{ + PCIESlot *s =3D PCIE_SLOT(obj); + + if (!s->speed) { + s->speed =3D QEMU_PCI_EXP_LNK_2_5GT; + } + + if (!s->width) { + s->width =3D QEMU_PCI_EXP_LNK_X1; + } +} + static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *dat= a) static const TypeInfo rp_info =3D { .name =3D TYPE_PCIE_ROOT_PORT, .parent =3D TYPE_PCIE_SLOT, + .instance_post_init =3D rp_instance_post_init, .class_init =3D rp_class_init, .abstract =3D true, .class_size =3D sizeof(PCIERootPortClass), diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0736014bfdb4..df242a0cafff 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -49,6 +49,10 @@ struct PCIESlot { /* pci express switch port with slot */ uint8_t chassis; uint16_t slot; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + QLIST_ENTRY(PCIESlot) next; }; =20 From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543942193260430.7745149535655; Tue, 4 Dec 2018 08:49:53 -0800 (PST) Received: from localhost ([::1]:57878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDtQ-00071A-3I for importer@patchew.org; Tue, 04 Dec 2018 11:49:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjA-0002ap-PQ for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDX0-0005dB-7w for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:45 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDX0-0005cz-0X for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:26:42 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5C7B113A9B; Tue, 4 Dec 2018 16:26:41 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id C5BE7600C4; Tue, 4 Dec 2018 16:26:34 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:34 -0700 Message-ID: <154394079441.28192.15583995529917119293.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 04 Dec 2018 16:26:41 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 5/9] pcie: Fill PCIESlot link fields to support higher speeds and widths X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Make use of the PCIESlot speed and width fields to update link information beyond those configured in pcie_cap_v1_fill(). This is only called for devices supporting a version 2 capability and automatically skips any non-PCIESlot devices. Only devices with increased link values generate any visible config space differences. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson --- hw/pci/pcie.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 61b7b96c52cd..556ec19925b9 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -27,6 +27,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pcie_regs.h" +#include "hw/pci/pcie_port.h" #include "qemu/range.h" =20 //#define DEBUG_PCIE @@ -87,6 +88,74 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t t= ype, uint8_t version) pci_set_word(cmask + PCI_EXP_LNKSTA, 0); } =20 +static void pcie_cap_fill_slot_lnk(PCIDevice *dev) +{ + PCIESlot *s =3D (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE= _SLOT); + uint8_t *exp_cap =3D dev->config + dev->exp.exp_cap; + + /* Skip anything that isn't a PCIESlot */ + if (!s) { + return; + } + + /* Clear and fill LNKCAP from what was configured above */ + pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, + QEMU_PCI_EXP_LNKCAP_MLW(s->width) | + QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); + + /* + * Link bandwidth notification is required for all root ports and + * downstream ports supporting links wider than x1. + */ + if (s->width > QEMU_PCI_EXP_LNK_X1) { + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_LBNC); + } + + if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { + /* + * Hot-plug capable downstream ports and downstream ports supporti= ng + * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLL= LARC + * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, wh= ich + * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also + * technically implement this, but it's not done here for compatib= ility. + */ + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_DLLLARC); + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, + PCI_EXP_LNKSTA_DLLLA); + + /* + * Target Link Speed defaults to the highest link speed supported = by + * the component. 2.5GT/s devices are permitted to hardwire to ze= ro. + */ + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, + PCI_EXP_LNKCTL2_TLS); + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, + QEMU_PCI_EXP_LNKCAP_MLS(s->speed) & + PCI_EXP_LNKCTL2_TLS); + } + + /* + * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is + * actually a reference to the highest bit supported in this register. + * We assume the device supports all link speeds. + */ + if (s->speed > QEMU_PCI_EXP_LNK_5GT) { + pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, + PCI_EXP_LNKCAP2_SLS_2_5GB | + PCI_EXP_LNKCAP2_SLS_5_0GB | + PCI_EXP_LNKCAP2_SLS_8_0GB); + if (s->speed > QEMU_PCI_EXP_LNK_8GT) { + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, + PCI_EXP_LNKCAP2_SLS_16_0GB); + } + } +} + int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port, Error **errp) @@ -108,6 +177,9 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, /* Filling values common with v1 */ pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); =20 + /* Fill link speed and width options */ + pcie_cap_fill_slot_lnk(dev); + /* Filling v2 specific values */ pci_set_long(exp_cap + PCI_EXP_DEVCAP2, PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 154394205538215.622581725636906; Tue, 4 Dec 2018 08:47:35 -0800 (PST) Received: from localhost ([::1]:57869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDr6-0005Rn-FN for importer@patchew.org; Tue, 04 Dec 2018 11:47:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjA-0002wM-CB for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDXL-0005tm-Q3 for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38800) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDXL-0005sp-Jm for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:03 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A4C96307D855; Tue, 4 Dec 2018 16:27:02 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id C06721054FD8; Tue, 4 Dec 2018 16:26:46 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:26:46 -0700 Message-ID: <154394080640.28192.18238093186084385391.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 04 Dec 2018 16:27:02 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 6/9] pcie: Allow generic PCIe root port to specify link speed and width X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Allow users to experimentally specify speed and width values for the generic PCIe root port. Defaults remain at 2.5GT/s & x1 for compatiblity with the intent to only support changing defaults via machine types for now. Note for libvirt testing that pcie-root-port controllers are given default names like "pci.7" which don't play well with using the "-set device.$name.$prop=3D$value" options accessible to us via options. The solution is to add an to the pcie-root-port , for example:
The "ua-" here is a mandatory prefix. We can then use: or, without an alias, set globals such as: Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/pci-bridge/gen_pcie_root_port.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index 299de429ec1e..ca5418a89dd2 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -124,6 +124,10 @@ static Property gen_rp_props[] =3D { res_reserve.mem_pref_32, -1), DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, + speed, PCIE_LINK_SPEED_2_5), + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, + width, PCIE_LINK_WIDTH_1), DEFINE_PROP_END_OF_LIST() }; =20 From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543942057461693.0918203579827; Tue, 4 Dec 2018 08:47:37 -0800 (PST) Received: from localhost ([::1]:57870 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDr8-0005TF-Pu for importer@patchew.org; Tue, 04 Dec 2018 11:47:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjA-0002mB-BF for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDXW-00064j-9Z for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53446) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDXU-0005zZ-KO for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:14 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5E33C13AA6; Tue, 4 Dec 2018 16:27:11 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1185E5C21C; Tue, 4 Dec 2018 16:27:08 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:27:07 -0700 Message-ID: <154394082769.28192.14712045129466115638.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 04 Dec 2018 16:27:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 7/9] vfio/pci: Remove PCIe Link Status emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Now that the downstream port will virtually negotiate itself to the link status of the downstream devie, we can remove this emulation. It's not clear that it was every terribly useful anyway. Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/vfio/pci.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 74f9a46b4be0..c0cb1ec28908 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1901,12 +1901,6 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, = int pos, uint8_t size, QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)= , ~0); vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); } - - /* Mark the Link Status bits as emulated to allow virtual negotiat= ion */ - vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, - pci_get_word(vdev->pdev.config + pos + - PCI_EXP_LNKSTA), - PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); } =20 /* From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543941885125178.74770577540176; Tue, 4 Dec 2018 08:44:45 -0800 (PST) Received: from localhost ([::1]:57841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDoQ-0002M3-Ow for importer@patchew.org; Tue, 04 Dec 2018 11:44:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDjA-0002cI-5d for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDXh-0006C5-3I for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:28 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49766) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDXg-0006AM-P1 for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:25 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 11BDA81F01; Tue, 4 Dec 2018 16:27:23 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id CBF2382799; Tue, 4 Dec 2018 16:27:16 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:27:16 -0700 Message-ID: <154394083644.28192.8501647946108201466.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 04 Dec 2018 16:27:23 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 8/9] q35/440fx/arm/spapr: Add QEMU 4.0 machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , "Michael S. Tsirkin" , Paolo Bonzini , David Gibson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Including all machine types that might have a pcie-root-port. Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Acked-by: David Gibson Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/arm/virt.c | 19 +++++++++++++++++-- hw/i386/pc_piix.c | 15 ++++++++++++--- hw/i386/pc_q35.c | 13 +++++++++++-- hw/ppc/spapr.c | 25 ++++++++++++++++++++++--- include/hw/compat.h | 3 +++ include/hw/i386/pc.h | 3 +++ 6 files changed, 68 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f69e7eb39977..beaf6bc43905 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1797,7 +1797,7 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 -static void virt_3_1_instance_init(Object *obj) +static void virt_4_0_instance_init(Object *obj) { VirtMachineState *vms =3D VIRT_MACHINE(obj); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); @@ -1867,10 +1867,25 @@ static void virt_3_1_instance_init(Object *obj) vms->irqmap =3D a15irqmap; } =20 +static void virt_machine_4_0_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(4, 0) + +#define VIRT_COMPAT_3_1 \ + HW_COMPAT_3_1 + +static void virt_3_1_instance_init(Object *obj) +{ + virt_4_0_instance_init(obj); +} + static void virt_machine_3_1_options(MachineClass *mc) { + virt_machine_4_0_options(mc); + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_1); } -DEFINE_VIRT_MACHINE_AS_LATEST(3, 1) +DEFINE_VIRT_MACHINE(3, 1) =20 #define VIRT_COMPAT_3_0 \ HW_COMPAT_3_0 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7092d6d13f66..cfaa83ee2fad 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -428,21 +428,30 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); } =20 -static void pc_i440fx_3_1_machine_options(MachineClass *m) +static void pc_i440fx_4_0_machine_options(MachineClass *m) { pc_i440fx_machine_options(m); m->alias =3D "pc"; m->is_default =3D 1; } =20 +DEFINE_I440FX_MACHINE(v4_0, "pc-i440fx-4.0", NULL, + pc_i440fx_4_0_machine_options); + +static void pc_i440fx_3_1_machine_options(MachineClass *m) +{ + pc_i440fx_4_0_machine_options(m); + m->is_default =3D 0; + m->alias =3D NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); +} + DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL, pc_i440fx_3_1_machine_options); =20 static void pc_i440fx_3_0_machine_options(MachineClass *m) { pc_i440fx_3_1_machine_options(m); - m->is_default =3D 0; - m->alias =3D NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); } =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4702bb13c472..e245db096dc1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -311,19 +311,28 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_3_1_machine_options(MachineClass *m) +static void pc_q35_4_0_machine_options(MachineClass *m) { pc_q35_machine_options(m); m->alias =3D "q35"; } =20 +DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, + pc_q35_4_0_machine_options); + +static void pc_q35_3_1_machine_options(MachineClass *m) +{ + pc_q35_4_0_machine_options(m); + m->alias =3D NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); +} + DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, pc_q35_3_1_machine_options); =20 static void pc_q35_3_0_machine_options(MachineClass *m) { pc_q35_3_1_machine_options(m); - m->alias =3D NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); } =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7afd1a175bf2..80d8498867a6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3956,19 +3956,38 @@ static const TypeInfo spapr_machine_info =3D { } \ type_init(spapr_machine_register_##suffix) =20 - /* +/* + * pseries-4.0 + */ +static void spapr_machine_4_0_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_4_0_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(4_0, "4.0", true); + +/* * pseries-3.1 */ +#define SPAPR_COMPAT_3_1 \ + HW_COMPAT_3_1 + static void spapr_machine_3_1_instance_options(MachineState *machine) { + spapr_machine_4_0_instance_options(machine); } =20 static void spapr_machine_3_1_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_3_1_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1); } =20 -DEFINE_SPAPR_MACHINE(3_1, "3.1", true); +DEFINE_SPAPR_MACHINE(3_1, "3.1", false); =20 /* * pseries-3.0 diff --git a/include/hw/compat.h b/include/hw/compat.h index 6f4d5fc64704..70958328fe7a 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H =20 +#define HW_COMPAT_3_1 \ + /* empty */ + #define HW_COMPAT_3_0 \ /* empty */ =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 136fe497b6b2..cb645bf368a3 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -294,6 +294,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); =20 +#define PC_COMPAT_3_1 \ + HW_COMPAT_3_1 \ + #define PC_COMPAT_3_0 \ HW_COMPAT_3_0 \ {\ From nobody Wed Apr 24 01:52:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543941877305271.5044197767661; Tue, 4 Dec 2018 08:44:37 -0800 (PST) Received: from localhost ([::1]:57838 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDoI-000284-V0 for importer@patchew.org; Tue, 04 Dec 2018 11:44:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUDj7-0002ZB-HQ for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:39:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUDXp-0006GP-Nn for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:34 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57724) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUDXp-0006Fw-IL for qemu-devel@nongnu.org; Tue, 04 Dec 2018 11:27:33 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E420829AC8; Tue, 4 Dec 2018 16:27:32 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 83B337EB61; Tue, 4 Dec 2018 16:27:28 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 04 Dec 2018 09:27:28 -0700 Message-ID: <154394084810.28192.18333845343054369357.stgit@gimli.home> In-Reply-To: <154393964026.28192.13536237934563059985.stgit@gimli.home> References: <154393964026.28192.13536237934563059985.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 04 Dec 2018 16:27:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v3 9/9] pcie: Fast PCIe root ports for new machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Change the default speed and width for new machine types to the fastest and widest currently supported. This should be compatible to the PCIe 4.0 spec. Pre-QEMU-4.0 machine types remain at 2.5GT/s, x1 width. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Signed-off-by: Alex Williamson Reviewed-by: Eric Auger --- hw/pci-bridge/gen_pcie_root_port.c | 4 ++-- include/hw/compat.h | 10 +++++++++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index ca5418a89dd2..9766edb44596 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -125,9 +125,9 @@ static Property gen_rp_props[] =3D { DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, - speed, PCIE_LINK_SPEED_2_5), + speed, PCIE_LINK_SPEED_16), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, - width, PCIE_LINK_WIDTH_1), + width, PCIE_LINK_WIDTH_32), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/include/hw/compat.h b/include/hw/compat.h index 70958328fe7a..702cc62277db 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -2,7 +2,15 @@ #define HW_COMPAT_H =20 #define HW_COMPAT_3_1 \ - /* empty */ + {\ + .driver =3D "pcie-root-port",\ + .property =3D "speed",\ + .value =3D "2_5",\ + },{\ + .driver =3D "pcie-root-port",\ + .property =3D "width",\ + .value =3D "1",\ + }, =20 #define HW_COMPAT_3_0 \ /* empty */