From nobody Thu Nov 6 22:56:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543857410885442.3283836578695; Mon, 3 Dec 2018 09:16:50 -0800 (PST) Received: from localhost ([::1]:50781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrpu-00020F-GM for importer@patchew.org; Mon, 03 Dec 2018 12:16:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42667) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTr5q-000651-A7 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:29:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTr5l-0003LU-0u for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:29:10 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59312) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gTr5i-0003K0-RD for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:29:03 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2B3EA3084049; Mon, 3 Dec 2018 16:29:01 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 872C263B88; Mon, 3 Dec 2018 16:28:51 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Mon, 03 Dec 2018 09:28:51 -0700 Message-ID: <154385453112.17724.5531705925756096220.stgit@gimli.home> In-Reply-To: <154385426086.17724.4390242199797858265.stgit@gimli.home> References: <154385426086.17724.4390242199797858265.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Mon, 03 Dec 2018 16:29:01 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v2 9/9] pcie: Fast PCIe root ports for new machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Change the default speed and width for new machine types to the fastest and widest currently supported. This should be compatible to the PCIe 4.0 spec. Pre-QEMU-4.0 machine types remain at 2.5GT/s, x1 width. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Signed-off-by: Alex Williamson --- hw/pci-bridge/gen_pcie_root_port.c | 4 ++-- include/hw/compat.h | 10 +++++++++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index e3bba2ab68ef..8e70c32a49ee 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -124,8 +124,8 @@ static Property gen_rp_props[] =3D { res_reserve.mem_pref_32, -1), DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), - DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot, speed, PCIE_LINK_SPEED_= 2_5), - DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot, width, PCIE_LINK_WIDTH_= 1), + DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot, speed, PCIE_LINK_SPEED_= 16), + DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot, width, PCIE_LINK_WIDTH_= 32), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/include/hw/compat.h b/include/hw/compat.h index 70958328fe7a..702cc62277db 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -2,7 +2,15 @@ #define HW_COMPAT_H =20 #define HW_COMPAT_3_1 \ - /* empty */ + {\ + .driver =3D "pcie-root-port",\ + .property =3D "speed",\ + .value =3D "2_5",\ + },{\ + .driver =3D "pcie-root-port",\ + .property =3D "width",\ + .value =3D "1",\ + }, =20 #define HW_COMPAT_3_0 \ /* empty */