From nobody Thu Nov 6 22:56:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543857229920697.6554602925098; Mon, 3 Dec 2018 09:13:49 -0800 (PST) Received: from localhost ([::1]:50747 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrn2-0007rd-4v for importer@patchew.org; Mon, 03 Dec 2018 12:13:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTr5Z-0005qD-6a for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTr5T-0003EO-Gx for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:53 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53672) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gTr5T-0003Dq-1Z for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:47 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 159BA3001DA4; Mon, 3 Dec 2018 16:28:46 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9F5C160E3F; Mon, 3 Dec 2018 16:28:36 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Mon, 03 Dec 2018 09:28:36 -0700 Message-ID: <154385451622.17724.12272989665681200621.stgit@gimli.home> In-Reply-To: <154385426086.17724.4390242199797858265.stgit@gimli.home> References: <154385426086.17724.4390242199797858265.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Mon, 03 Dec 2018 16:28:46 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v2 8/9] q35/440fx/arm/spapr: Add QEMU 4.0 machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , "Michael S. Tsirkin" , Paolo Bonzini , David Gibson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Including all machine types that might have a pcie-root-port. Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: David Gibson Signed-off-by: Alex Williamson --- hw/arm/virt.c | 19 +++++++++++++++++-- hw/i386/pc_piix.c | 15 ++++++++++++--- hw/i386/pc_q35.c | 13 +++++++++++-- hw/ppc/spapr.c | 25 ++++++++++++++++++++++--- include/hw/compat.h | 3 +++ include/hw/i386/pc.h | 3 +++ 6 files changed, 68 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f69e7eb39977..beaf6bc43905 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1797,7 +1797,7 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 -static void virt_3_1_instance_init(Object *obj) +static void virt_4_0_instance_init(Object *obj) { VirtMachineState *vms =3D VIRT_MACHINE(obj); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); @@ -1867,10 +1867,25 @@ static void virt_3_1_instance_init(Object *obj) vms->irqmap =3D a15irqmap; } =20 +static void virt_machine_4_0_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(4, 0) + +#define VIRT_COMPAT_3_1 \ + HW_COMPAT_3_1 + +static void virt_3_1_instance_init(Object *obj) +{ + virt_4_0_instance_init(obj); +} + static void virt_machine_3_1_options(MachineClass *mc) { + virt_machine_4_0_options(mc); + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_1); } -DEFINE_VIRT_MACHINE_AS_LATEST(3, 1) +DEFINE_VIRT_MACHINE(3, 1) =20 #define VIRT_COMPAT_3_0 \ HW_COMPAT_3_0 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7092d6d13f66..cfaa83ee2fad 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -428,21 +428,30 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); } =20 -static void pc_i440fx_3_1_machine_options(MachineClass *m) +static void pc_i440fx_4_0_machine_options(MachineClass *m) { pc_i440fx_machine_options(m); m->alias =3D "pc"; m->is_default =3D 1; } =20 +DEFINE_I440FX_MACHINE(v4_0, "pc-i440fx-4.0", NULL, + pc_i440fx_4_0_machine_options); + +static void pc_i440fx_3_1_machine_options(MachineClass *m) +{ + pc_i440fx_4_0_machine_options(m); + m->is_default =3D 0; + m->alias =3D NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); +} + DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL, pc_i440fx_3_1_machine_options); =20 static void pc_i440fx_3_0_machine_options(MachineClass *m) { pc_i440fx_3_1_machine_options(m); - m->is_default =3D 0; - m->alias =3D NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); } =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4702bb13c472..e245db096dc1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -311,19 +311,28 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_3_1_machine_options(MachineClass *m) +static void pc_q35_4_0_machine_options(MachineClass *m) { pc_q35_machine_options(m); m->alias =3D "q35"; } =20 +DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, + pc_q35_4_0_machine_options); + +static void pc_q35_3_1_machine_options(MachineClass *m) +{ + pc_q35_4_0_machine_options(m); + m->alias =3D NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); +} + DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, pc_q35_3_1_machine_options); =20 static void pc_q35_3_0_machine_options(MachineClass *m) { pc_q35_3_1_machine_options(m); - m->alias =3D NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); } =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7afd1a175bf2..80d8498867a6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3956,19 +3956,38 @@ static const TypeInfo spapr_machine_info =3D { } \ type_init(spapr_machine_register_##suffix) =20 - /* +/* + * pseries-4.0 + */ +static void spapr_machine_4_0_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_4_0_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(4_0, "4.0", true); + +/* * pseries-3.1 */ +#define SPAPR_COMPAT_3_1 \ + HW_COMPAT_3_1 + static void spapr_machine_3_1_instance_options(MachineState *machine) { + spapr_machine_4_0_instance_options(machine); } =20 static void spapr_machine_3_1_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_3_1_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1); } =20 -DEFINE_SPAPR_MACHINE(3_1, "3.1", true); +DEFINE_SPAPR_MACHINE(3_1, "3.1", false); =20 /* * pseries-3.0 diff --git a/include/hw/compat.h b/include/hw/compat.h index 6f4d5fc64704..70958328fe7a 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H =20 +#define HW_COMPAT_3_1 \ + /* empty */ + #define HW_COMPAT_3_0 \ /* empty */ =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 136fe497b6b2..cb645bf368a3 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -294,6 +294,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); =20 +#define PC_COMPAT_3_1 \ + HW_COMPAT_3_1 \ + #define PC_COMPAT_3_0 \ HW_COMPAT_3_0 \ {\