From nobody Thu Nov 6 22:55:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543857068047675.9609534759809; Mon, 3 Dec 2018 09:11:08 -0800 (PST) Received: from localhost ([::1]:50721 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrkI-0004bm-BD for importer@patchew.org; Mon, 03 Dec 2018 12:10:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTr59-0005Ti-2Q for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTr58-000350-C3 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:27 -0500 Received: from mx1.redhat.com ([209.132.183.28]:54714) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gTr58-00034b-3K for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:26 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5A28B30024EC; Mon, 3 Dec 2018 16:28:25 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id 046F55D6B3; Mon, 3 Dec 2018 16:28:20 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Mon, 03 Dec 2018 09:28:20 -0700 Message-ID: <154385450060.17724.13002565063457905823.stgit@gimli.home> In-Reply-To: <154385426086.17724.4390242199797858265.stgit@gimli.home> References: <154385426086.17724.4390242199797858265.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Mon, 03 Dec 2018 16:28:25 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v2 6/9] pcie: Allow generic PCIe root port to specify link speed and width X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Allow users to specify speed and width values for the generic PCIe root port. Defaults remain at 2.5GT/s & x1 for compatiblity. Note for libvirt testing that pcie-root-port controllers are given default names like "pci.7" which don't play well with using the "-set device.$name.$prop=3D$value" options accessible to us via options. The solution is to add an to the pcie-root-port , for example:
The "ua-" here is a mandatory prefix. We can then use: or, without an alias, set globals such as: Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson --- hw/pci-bridge/gen_pcie_root_port.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index 299de429ec1e..e3bba2ab68ef 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -124,6 +124,8 @@ static Property gen_rp_props[] =3D { res_reserve.mem_pref_32, -1), DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), + DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot, speed, PCIE_LINK_SPEED_= 2_5), + DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot, width, PCIE_LINK_WIDTH_= 1), DEFINE_PROP_END_OF_LIST() }; =20