From nobody Thu Nov 6 22:56:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543857086777492.73560260036504; Mon, 3 Dec 2018 09:11:26 -0800 (PST) Received: from localhost ([::1]:50727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrke-0004y1-Cs for importer@patchew.org; Mon, 03 Dec 2018 12:11:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTr4t-0005I7-1j for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTr4o-0002tj-3A for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:11 -0500 Received: from mx1.redhat.com ([209.132.183.28]:43754) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gTr4n-0002tH-U3 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:28:06 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 40DF73DE2F; Mon, 3 Dec 2018 16:28:05 +0000 (UTC) Received: from gimli.home (ovpn-116-92.phx2.redhat.com [10.3.116.92]) by smtp.corp.redhat.com (Postfix) with ESMTP id E419B5D772; Mon, 3 Dec 2018 16:27:59 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Mon, 03 Dec 2018 09:27:59 -0700 Message-ID: <154385447950.17724.6774925668661407225.stgit@gimli.home> In-Reply-To: <154385426086.17724.4390242199797858265.stgit@gimli.home> References: <154385426086.17724.4390242199797858265.stgit@gimli.home> User-Agent: StGit/0.19-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 03 Dec 2018 16:28:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [for-4.0 PATCH v2 4/9] pcie: Add link speed and width fields to PCIESlot X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geoffrey McRae , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Add fields allowing the PCIe link speed and width of a PCIESlot to be configured, with an instance_post_init callback on the root port parent class to set defaults. This allows child classes to set these via properties or via their own instance_init callback, without requiring all implementions to support arbitrary user selected values. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Tested-by: Geoffrey McRae Signed-off-by: Alex Williamson --- hw/pci-bridge/pcie_root_port.c | 14 ++++++++++++++ include/hw/pci/pcie_port.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8cd4a36..34ad76743c44 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -140,6 +140,19 @@ static Property rp_props[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +static void rp_instance_post_init(Object *obj) +{ + PCIESlot *s =3D PCIE_SLOT(obj); + + if (!s->speed) { + s->speed =3D QEMU_PCI_EXP_LNK_2_5GT; + } + + if (!s->width) { + s->width =3D QEMU_PCI_EXP_LNK_X1; + } +} + static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *dat= a) static const TypeInfo rp_info =3D { .name =3D TYPE_PCIE_ROOT_PORT, .parent =3D TYPE_PCIE_SLOT, + .instance_post_init =3D rp_instance_post_init, .class_init =3D rp_class_init, .abstract =3D true, .class_size =3D sizeof(PCIERootPortClass), diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0736014bfdb4..df242a0cafff 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -49,6 +49,10 @@ struct PCIESlot { /* pci express switch port with slot */ uint8_t chassis; uint16_t slot; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + QLIST_ENTRY(PCIESlot) next; }; =20