From nobody Thu Nov 6 18:27:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542470478199391.2601547362616; Sat, 17 Nov 2018 08:01:18 -0800 (PST) Received: from localhost ([::1]:49710 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gO325-00082U-1M for importer@patchew.org; Sat, 17 Nov 2018 11:01:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gO2x0-0003xG-Kp for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:56:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gO2wx-0000fu-96 for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:56:02 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:60343 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gO2ww-00077S-UV for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:55:59 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8942F1A20B5; Sat, 17 Nov 2018 16:54:55 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5E6A01A2057; Sat, 17 Nov 2018 16:54:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sat, 17 Nov 2018 16:54:32 +0100 Message-Id: <1542470080-5797-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542470080-5797-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1542470080-5797-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 03/11] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Fredrik Noring DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic gen_muldiv. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 59 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8601333..3ddd700 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4743,6 +4743,63 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc= , int rd, int rs, int rt) tcg_temp_free(t1); } =20 +static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case TX79_MMI_DIV1: + { + TCGv t2 =3D tcg_temp_new(); + TCGv t3 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_div_tl(cpu_LO[1], t0, t1); + tcg_gen_rem_tl(cpu_HI[1], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); + tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); + tcg_temp_free(t3); + tcg_temp_free(t2); + } + break; + case TX79_MMI_DIVU1: + { + TCGv t2 =3D tcg_const_tl(0); + TCGv t3 =3D tcg_const_tl(1); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_divu_tl(cpu_LO[1], t0, t1); + tcg_gen_remu_tl(cpu_HI[1], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); + tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); + tcg_temp_free(t3); + tcg_temp_free(t2); + } + break; + default: + MIPS_INVAL("div1 TX79"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + static void gen_muldiv(DisasContext *ctx, uint32_t opc, int acc, int rs, int rt) { @@ -4755,14 +4812,11 @@ static void gen_muldiv(DisasContext *ctx, uint32_t = opc, gen_load_gpr(t1, rt); =20 if (acc !=3D 0) { - if (!(ctx->insn_flags & INSN_R5900)) { - check_dsp(ctx); - } + check_dsp(ctx); } =20 switch (opc) { case OPC_DIV: - case TX79_MMI_DIV1: { TCGv t2 =3D tcg_temp_new(); TCGv t3 =3D tcg_temp_new(); @@ -4784,7 +4838,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, } break; case OPC_DIVU: - case TX79_MMI_DIVU1: { TCGv t2 =3D tcg_const_tl(0); TCGv t3 =3D tcg_const_tl(1); @@ -26525,7 +26578,7 @@ static void decode_tx79_mmi(CPUMIPSState *env, Disa= sContext *ctx) break; case TX79_MMI_DIV1: case TX79_MMI_DIVU1: - gen_muldiv(ctx, opc, 1, rs, rt); + gen_div1_tx79(ctx, opc, rs, rt); break; case TX79_MMI_MTLO1: case TX79_MMI_MTHI1: --=20 2.7.4