From nobody Thu Nov 6 18:27:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542470478950816.5218152268706; Sat, 17 Nov 2018 08:01:18 -0800 (PST) Received: from localhost ([::1]:49709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gO325-000828-Q6 for importer@patchew.org; Sat, 17 Nov 2018 11:01:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gO2x0-0003xF-KR for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:56:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gO2wx-0000g6-Ac for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:56:02 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:60340 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gO2ww-00077R-UW for qemu-devel@nongnu.org; Sat, 17 Nov 2018 10:55:59 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8081A1A2064; Sat, 17 Nov 2018 16:54:55 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 56F351A204A; Sat, 17 Nov 2018 16:54:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sat, 17 Nov 2018 16:54:31 +0100 Message-Id: <1542470080-5797-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542470080-5797-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1542470080-5797-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 02/11] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Fredrik Noring MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of the generic gen_HILO. Reviewed-by: Aleksandar Markovic Signed-off-by: Fredrik Noring --- target/mips/translate.c | 51 ++++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 60320cb..8601333 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4359,24 +4359,56 @@ static void gen_shift(DisasContext *ctx, uint32_t o= pc, tcg_temp_free(t1); } =20 +/* Copy GPR to and from TX79 HI1/LO1 register. */ +static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) +{ + if (reg =3D=3D 0 && (opc =3D=3D TX79_MMI_MFHI1 || opc =3D=3D TX79_MMI_= MFLO1)) { + /* Treat as NOP. */ + return; + } + + switch (opc) { + case TX79_MMI_MFHI1: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); + break; + case TX79_MMI_MFLO1: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); + break; + case TX79_MMI_MTHI1: + if (reg !=3D 0) { + tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); + } else { + tcg_gen_movi_tl(cpu_HI[1], 0); + } + break; + case TX79_MMI_MTLO1: + if (reg !=3D 0) { + tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); + } else { + tcg_gen_movi_tl(cpu_LO[1], 0); + } + break; + default: + MIPS_INVAL("mfthilo1 TX79"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D TX79_MMI_MFHI1 = || - opc =3D=3D OPC_MFLO || opc =3D=3D TX79_MMI_MFLO1)) { + if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D OPC_MFLO)) { /* Treat as NOP. */ return; } =20 if (acc !=3D 0) { - if (!(ctx->insn_flags & INSN_R5900)) { - check_dsp(ctx); - } + check_dsp(ctx); } =20 switch (opc) { case OPC_MFHI: - case TX79_MMI_MFHI1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); @@ -4387,7 +4419,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MFLO: - case TX79_MMI_MFLO1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); @@ -4398,7 +4429,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTHI: - case TX79_MMI_MTHI1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -4413,7 +4443,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTLO: - case TX79_MMI_MTLO1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -26500,11 +26529,11 @@ static void decode_tx79_mmi(CPUMIPSState *env, Di= sasContext *ctx) break; case TX79_MMI_MTLO1: case TX79_MMI_MTHI1: - gen_HILO(ctx, opc, 1, rs); + gen_HILO1_tx79(ctx, opc, rs); break; case TX79_MMI_MFLO1: case TX79_MMI_MFHI1: - gen_HILO(ctx, opc, 1, rd); + gen_HILO1_tx79(ctx, opc, rd); break; case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */ --=20 2.7.4