From nobody Thu Nov 6 18:26:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542228780519576.3674491678164; Wed, 14 Nov 2018 12:53:00 -0800 (PST) Received: from localhost ([::1]:34167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gN29j-0005Mz-GT for importer@patchew.org; Wed, 14 Nov 2018 15:52:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gN283-0004WJ-O0 for qemu-devel@nongnu.org; Wed, 14 Nov 2018 15:51:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gN281-0004zM-1z for qemu-devel@nongnu.org; Wed, 14 Nov 2018 15:51:15 -0500 Received: from mx1.redhat.com ([209.132.183.28]:35156) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gN280-0004z8-SZ for qemu-devel@nongnu.org; Wed, 14 Nov 2018 15:51:13 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 259D35D697; Wed, 14 Nov 2018 20:51:12 +0000 (UTC) Received: from gimli.home (ovpn-116-133.phx2.redhat.com [10.3.116.133]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4161D600D6; Wed, 14 Nov 2018 20:51:06 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 13:51:05 -0700 Message-ID: <154222866587.9288.1217475364900572268.stgit@gimli.home> In-Reply-To: <154222737752.9288.484557356059052047.stgit@gimli.home> References: <154222737752.9288.484557356059052047.stgit@gimli.home> User-Agent: StGit/0.18-136-gffd7-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Wed, 14 Nov 2018 20:51:12 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC for-3.2 PATCH 4/7] pcie: Add link speed and width fields to PCIESlot X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: geoff@hostfission.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Add fields allowing the PCIe link speed and width of a PCIESlot to be configured, with an instance_post_init callback on the root port parent class to set defaults. This allows child classes to via properties, without requiring all implementions to support arbitrary user selected values, and also allows child class instance_init callbacks to set defaults, for example using a machine defined link default. Signed-off-by: Alex Williamson --- hw/pci-bridge/pcie_root_port.c | 14 ++++++++++++++ include/hw/pci/pcie_port.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8cd4a36..34ad76743c44 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -140,6 +140,19 @@ static Property rp_props[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +static void rp_instance_post_init(Object *obj) +{ + PCIESlot *s =3D PCIE_SLOT(obj); + + if (!s->speed) { + s->speed =3D QEMU_PCI_EXP_LNK_2_5GT; + } + + if (!s->width) { + s->width =3D QEMU_PCI_EXP_LNK_X1; + } +} + static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *dat= a) static const TypeInfo rp_info =3D { .name =3D TYPE_PCIE_ROOT_PORT, .parent =3D TYPE_PCIE_SLOT, + .instance_post_init =3D rp_instance_post_init, .class_init =3D rp_class_init, .abstract =3D true, .class_size =3D sizeof(PCIERootPortClass), diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0736014bfdb4..df242a0cafff 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -49,6 +49,10 @@ struct PCIESlot { /* pci express switch port with slot */ uint8_t chassis; uint16_t slot; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + QLIST_ENTRY(PCIESlot) next; }; =20