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[80.66.210.96]) by smtp.gmail.com with ESMTPSA id y19sm5478737wmj.2.2018.11.14.02.56.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=JUdUD+YhsYNwA7UqdptYtOmTpt+DoJexbYK9RmQ1lg0=; b=G06WcAbhGdGH04AmNspRKW6O9zN26MMZs9lm7zCtKNUUgsweR8dG94iJGw5dzy+oGv TAQRdR/jGymMm+SttOTWR+Oib1zVO/RwUH6sDqcfGLO7Du1u26e88fXS287MD3j9w11w lXekCZU81gc/GWL1RFKqARkcwzsX+4v3dhvFJYD6ffoSzD/opWKnwRaAbSJ5xBOWJD+o ZS1HOjJ7P3op5Kc+Vw3Ep7oc9Z1VyHa9StWDrKxMKILqAcSvMUs6Z0IRrV76ZsXIYFRj 5bliieNbZCNgA1+TN2Yo91zKxYQvr6gG/m3QZ7LCsK5Zej+ItB4OUXOgbAz2tKBLn9Q5 DZ9g== X-Gm-Message-State: AGRZ1gITHn08O2yU8a6GkdxAp+Viu6RqcjRVnFWG9W0oGIOec1bCahZ2 0Vuhzsb+/eE+JTQ+SPz1HNg= X-Google-Smtp-Source: AJdET5d9cfc/ELZAHfDsM3/GiNBdQ40jXcDf4I+l2p69OvYg/trU/7M1T1UqvFDU34nAzrvS3b238g== X-Received: by 2002:a1c:6555:: with SMTP id z82-v6mr1503964wmb.66.1542193013904; Wed, 14 Nov 2018 02:56:53 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:57:09 +0100 Message-ID: <154219302946.19470.14979106134197499918.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.65 Subject: [Qemu-devel] [RFC PATCH 3/3] i386: custom cache size in AMD's CPUID descriptors too X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" If specified on the command line, alter the cache size(s) properties accordingly, before encoding them in the AMD's CPUID cache descriptors too (i.e., 80000006 and 8000001d). Signed-off-by: Dario Faggioli --- Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 17aff19561..4949d6b907 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4490,6 +4490,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size); + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size); encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL, @@ -4546,10 +4552,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, eax, ebx, ecx, edx); break;