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[80.66.210.96]) by smtp.gmail.com with ESMTPSA id x2-v6sm15019671wrw.42.2018.11.14.02.56.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=S0twy0PVPP3duPNkDv9U15J+RGIRtaCPW0bjLDfEDC4=; b=i6+4ZEYhsI2oY8NJs/JiJ0MdtiZXQTOKCWwZwB//Ili90bJE5AtRa0UbDb+tu1/SNC rXeQWS2x/CWhBBcF359/GqGMgBucfAiZxjweAsH2PqBCYGVB9VqAKJ84FTvugavNoM9G USBzxTUmyuA5E+VTNmlG8SsvgLK8cgLM70eZZFibgFr5ANd/N+BK0HbkNzVeK5+EOYZS RYFdJE9QcX5JmbGKc4AU/3aoKCN+F0SmmUjWlZ4Q3RWPZdMHvsu3TzeRqTqkOmIlH04V 8JfjjMV/58VyhffplMsvNyhxr3Bj4o0EAcnBIvaZmYrOYWaOtIipWdlJHDMgpLBSUC2c yqdw== X-Gm-Message-State: AGRZ1gKNgaYsjB9JyIy1VA9lMM4IudxBWOouX/9DMQIOLxWwZRc6hbjo flmZKPAgVQ9T+2JpQPHGmV8= X-Google-Smtp-Source: AJdET5fuwt7fMcH9Ha8doxD4DD4Z51vPz9cHoiaMA4SR4VxpxlE20Pf1bIPd4UnldxJbqkRTikUXxA== X-Received: by 2002:a7b:c083:: with SMTP id r3-v6mr1463036wmh.101.1542192999095; Wed, 14 Nov 2018 02:56:39 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:56:54 +0100 Message-ID: <154219301447.19470.4834273682384554888.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.66 Subject: [Qemu-devel] [RFC PATCH 1/3] i386: add properties for customizing L2 and L3 caches size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Make it possible to specify a custom size for the L2 and L3 caches, from the command line. This can be useful in cases where applications or libraries check, within the guest, the cache size and behave differently depending on what they actually see. Signed-off-by: Dario Faggioli --- I am not entirely sure I got the include/hw/i386 bits right (i.e., whether I should include the new properties in PC_COMPAT_3_0 and, if yes, if the stanzas are correct). I'll dig further (and accept any help/advice :-D ) --- Cc: "Michael S. Tsirkin" Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 136fe497b6..1094bba68c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -308,6 +308,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_= t *); .driver =3D "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\ .property =3D "pku",\ .value =3D "off",\ + },{\ + .driver =3D TYPE_X86_CPU,\ + .property =3D "l3-cache-size",\ + .value =3D "off",\ + },{\ + .driver =3D TYPE_X86_CPU,\ + .property =3D "l2-cache-size",\ + .value =3D "off",\ }, =20 #define PC_COMPAT_2_12 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f81d35e1f9..b8ccb2be04 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5778,6 +5778,14 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, false), + + /* + * Custom size for L2 and/or L3 cache. Default (0) means we use the + * default value for the CPU. + */ + DEFINE_PROP_SIZE("l2-cache-size", X86CPU, l2_cache_size, 0), + DEFINE_PROP_SIZE("l3-cache-size", X86CPU, l3_cache_size, 0), + DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9c52d0cbeb..ba0b913448 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1476,6 +1476,9 @@ struct X86CPU { int32_t core_id; int32_t thread_id; =20 + uint64_t l2_cache_size; + uint64_t l3_cache_size; + int32_t hv_max_vps; }; =20