From nobody Wed Nov 5 10:42:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540558671307889.7314472790371; Fri, 26 Oct 2018 05:57:51 -0700 (PDT) Received: from localhost ([::1]:59968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gG1gT-0001Ee-Qy for importer@patchew.org; Fri, 26 Oct 2018 08:57:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gG1en-0000KJ-Ev for qemu-devel@nongnu.org; Fri, 26 Oct 2018 08:56:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gG1em-0006hk-7e for qemu-devel@nongnu.org; Fri, 26 Oct 2018 08:56:05 -0400 Received: from mga14.intel.com ([192.55.52.115]:32031) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gG1el-0006es-Vw for qemu-devel@nongnu.org; Fri, 26 Oct 2018 08:56:04 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2018 05:56:03 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga002.jf.intel.com with ESMTP; 26 Oct 2018 05:56:02 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,427,1534834800"; d="scan'208";a="103508562" From: Robert Hoo To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Fri, 26 Oct 2018 20:55:55 +0800 Message-Id: <1540558555-75679-4-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1540558555-75679-1-git-send-email-robert.hu@linux.intel.com> References: <1540558555-75679-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH v6 3/3] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, qemu-devel@nongnu.org, Robert Hoo Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note RSBA is specially treated -- no matter host support it or not, qemu pretends it is supported. Changes in v6: filter out MSR features whose dependent CPUID enumeration is= not there. Signed-off-by: Robert Hoo Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 31 ++++++++++++++++++++++++++++++- target/i386/cpu.h | 8 ++++++++ target/i386/kvm.c | 11 +++++++++++ 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0de21fa..6371722 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1141,6 +1141,27 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D ~0U, }, + /*Below are MSR exposed features*/ + [FEAT_ARCH_CAPABILITIES] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", + "ssb-no", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_ARCH_CAPABILITIES, + .cpuid_dep =3D { + FEAT_7_0_EDX, + CPUID_7_0_EDX_ARCH_CAPABILITIES + } + }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -3696,7 +3717,15 @@ static uint32_t x86_cpu_get_supported_feature_word(F= eatureWord w, wi->cpuid.reg); break; case MSR_FEATURE_WORD: - r =3D kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.in= dex); + /* Special case: + * No matter host status, IA32_ARCH_CAPABILITIES.RSBA [bit 2] + * is always supported in guest. + */ + if (wi->msr.index =3D=3D MSR_IA32_ARCH_CAPABILITIES) { + r =3D MSR_ARCH_CAP_RSBA; + } + r |=3D kvm_arch_get_supported_msr_feature(kvm_state, + wi->msr.index); break; } } else if (hvf_enabled()) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index dd3de97..ff1ae32 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -507,6 +507,7 @@ typedef enum FeatureWord { FEAT_XSAVE_COMP_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ MSR_FEATURE_WORD_BEGIN, /* Define MSR feature words below */ + FEAT_ARCH_CAPABILITIES =3D MSR_FEATURE_WORD_BEGIN, FEATURE_WORDS, } FeatureWord; =20 @@ -735,6 +736,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) =20 +/* MSR Feature Bits */ +#define MSR_ARCH_CAP_RDCL_NO (1U << 0) +#define MSR_ARCH_CAP_IBRS_ALL (1U << 1) +#define MSR_ARCH_CAP_RSBA (1U << 2) +#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) +#define MSR_ARCH_CAP_SSB_NO (1U << 4) + #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF #endif diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 161fc38..796a049 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1975,6 +1975,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } #endif =20 + /* If host supports feature MSR, write down. */ + if (kvm_feature_msrs) { + int i; + for (i =3D 0; i < kvm_feature_msrs->nmsrs; i++) + if (kvm_feature_msrs->indices[i] =3D=3D MSR_IA32_ARCH_CAPABILI= TIES) { + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, + env->features[FEAT_ARCH_CAPABILITIES]); + break; + } + } + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. --=20 1.8.3.1