From nobody Thu Nov 6 10:30:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154038866713694.36597346326403; Wed, 24 Oct 2018 06:44:27 -0700 (PDT) Received: from localhost ([::1]:48533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJST-0006M1-T6 for importer@patchew.org; Wed, 24 Oct 2018 09:44:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJQK-0004sG-Dg for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFJQE-0001lS-1U for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:12 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48994 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFJQC-0001H7-7d for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:05 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1A5BC1A4563; Wed, 24 Oct 2018 15:40:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id E7D1E1A456F; Wed, 24 Oct 2018 15:40:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 15:40:18 +0200 Message-Id: <1540388447-27062-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Fredrik Noring Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of instructions in MMI class. Reviewed-by: Aleksandar Markovic Signed-off-by: Fredrik Noring Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e205c3e..ae98817 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2129,6 +2129,57 @@ enum { TX79_SQ =3D 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; =20 +/* + * TX79 Multimedia Instructions with opcode field =3D MMI: + * + * 31 26 5 0 + * +--------+-------------------------------+--------+ + * | MMI | |function| + * +--------+-------------------------------+--------+ + * + * function bits 2..0 + * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 + * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 + * -------+-------+-------+-------+-------+-------+-------+-------+-----= -- + * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | * + * 1 001 | MMI0% | MMI2% | * | * | * | * | * | * + * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | * + * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | * + * 4 100 | MADD1 | MADDU1| * | * | * | * | * | * + * 5 101 | MMI1% | MMI3% | * | * | * | * | * | * + * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH + * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW + */ + +#define MASK_TX79_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) +enum { + TX79_MMI_MADD =3D 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */ + TX79_MMI_MADDU =3D 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */ + TX79_MMI_PLZCW =3D 0x04 | TX79_CLASS_MMI, + TX79_MMI_CLASS_MMI0 =3D 0x08 | TX79_CLASS_MMI, + TX79_MMI_CLASS_MMI2 =3D 0x09 | TX79_CLASS_MMI, + TX79_MMI_MFHI1 =3D 0x10 | TX79_CLASS_MMI, /* Same minor as OPC_MF= HI */ + TX79_MMI_MTHI1 =3D 0x11 | TX79_CLASS_MMI, /* Same minor as OPC_MT= HI */ + TX79_MMI_MFLO1 =3D 0x12 | TX79_CLASS_MMI, /* Same minor as OPC_MF= LO */ + TX79_MMI_MTLO1 =3D 0x13 | TX79_CLASS_MMI, /* Same minor as OPC_MT= LO */ + TX79_MMI_MULT1 =3D 0x18 | TX79_CLASS_MMI, /* Same minor as OPC_MU= LT */ + TX79_MMI_MULTU1 =3D 0x19 | TX79_CLASS_MMI, /* Same minor as OPC_MU= LTU */ + TX79_MMI_DIV1 =3D 0x1A | TX79_CLASS_MMI, /* Same minor as OPC_DI= V */ + TX79_MMI_DIVU1 =3D 0x1B | TX79_CLASS_MMI, /* Same minor as OPC_DI= VU */ + TX79_MMI_MADD1 =3D 0x20 | TX79_CLASS_MMI, + TX79_MMI_MADDU1 =3D 0x21 | TX79_CLASS_MMI, + TX79_MMI_CLASS_MMI1 =3D 0x28 | TX79_CLASS_MMI, + TX79_MMI_CLASS_MMI3 =3D 0x29 | TX79_CLASS_MMI, + TX79_MMI_PMFHL =3D 0x30 | TX79_CLASS_MMI, + TX79_MMI_PMTHL =3D 0x31 | TX79_CLASS_MMI, + TX79_MMI_PSLLH =3D 0x34 | TX79_CLASS_MMI, + TX79_MMI_PSRLH =3D 0x36 | TX79_CLASS_MMI, + TX79_MMI_PSRAH =3D 0x37 | TX79_CLASS_MMI, + TX79_MMI_PSLLW =3D 0x3C | TX79_CLASS_MMI, + TX79_MMI_PSRLW =3D 0x3E | TX79_CLASS_MMI, + TX79_MMI_PSRAW =3D 0x3F | TX79_CLASS_MMI, +}; + /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; --=20 2.7.4