From nobody Thu Nov 6 10:38:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540390356479918.988724078465; Wed, 24 Oct 2018 07:12:36 -0700 (PDT) Received: from localhost ([::1]:48682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJtc-0000ln-9E for importer@patchew.org; Wed, 24 Oct 2018 10:12:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJQk-0005JQ-HY for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFJQi-00026R-D1 for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:50093 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFJQi-0001yd-0A for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A87301A452A; Wed, 24 Oct 2018 15:40:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 456D81A4590; Wed, 24 Oct 2018 15:40:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 15:40:47 +0200 Message-Id: <1540388447-27062-34-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 33/33] target/mips: Fix decoding of ALIGN and DALIGN instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to allow paremeter 'bp' to occupy two and three bits, respectively. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 40 ++++++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index fa29c1e..c44a751 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -463,8 +463,10 @@ enum { OPC_WSBH =3D (0x02 << 6) | OPC_BSHFL, OPC_SEB =3D (0x10 << 6) | OPC_BSHFL, OPC_SEH =3D (0x18 << 6) | OPC_BSHFL, - OPC_ALIGN =3D (0x08 << 6) | OPC_BSHFL, /* 010.bp */ - OPC_ALIGN_END =3D (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */ + OPC_ALIGN =3D (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11= ) */ + OPC_ALIGN_1 =3D (0x09 << 6) | OPC_BSHFL, + OPC_ALIGN_2 =3D (0x0A << 6) | OPC_BSHFL, + OPC_ALIGN_3 =3D (0x0B << 6) | OPC_BSHFL, OPC_BITSWAP =3D (0x00 << 6) | OPC_BSHFL /* 00000 */ }; =20 @@ -474,8 +476,14 @@ enum { enum { OPC_DSBH =3D (0x02 << 6) | OPC_DBSHFL, OPC_DSHD =3D (0x05 << 6) | OPC_DBSHFL, - OPC_DALIGN =3D (0x08 << 6) | OPC_DBSHFL, /* 01.bp */ - OPC_DALIGN_END =3D (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */ + OPC_DALIGN =3D (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.11= 1) */ + OPC_DALIGN_1 =3D (0x09 << 6) | OPC_DBSHFL, + OPC_DALIGN_2 =3D (0x0A << 6) | OPC_DBSHFL, + OPC_DALIGN_3 =3D (0x0B << 6) | OPC_DBSHFL, + OPC_DALIGN_4 =3D (0x0C << 6) | OPC_DBSHFL, + OPC_DALIGN_5 =3D (0x0D << 6) | OPC_DBSHFL, + OPC_DALIGN_6 =3D (0x0E << 6) | OPC_DBSHFL, + OPC_DALIGN_7 =3D (0x0F << 6) | OPC_DBSHFL, OPC_DBITSWAP =3D (0x00 << 6) | OPC_DBSHFL, /* 00000 */ }; =20 @@ -23957,7 +23965,9 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) op2 =3D MASK_BSHFL(ctx->opcode); switch (op2) { case OPC_ALIGN: - case OPC_ALIGN_END: + case OPC_ALIGN_1: + case OPC_ALIGN_2: + case OPC_ALIGN_3: gen_align(ctx, 32, rd, rs, rt, sa & 3); break; case OPC_BITSWAP: @@ -23983,7 +23993,13 @@ static void decode_opc_special3_r6(CPUMIPSState *e= nv, DisasContext *ctx) op2 =3D MASK_DBSHFL(ctx->opcode); switch (op2) { case OPC_DALIGN: - case OPC_DALIGN_END: + case OPC_DALIGN_1: + case OPC_DALIGN_2: + case OPC_DALIGN_3: + case OPC_DALIGN_4: + case OPC_DALIGN_5: + case OPC_DALIGN_6: + case OPC_DALIGN_7: gen_align(ctx, 64, rd, rs, rt, sa & 7); break; case OPC_DBITSWAP: @@ -24843,7 +24859,9 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) op2 =3D MASK_BSHFL(ctx->opcode); switch (op2) { case OPC_ALIGN: - case OPC_ALIGN_END: + case OPC_ALIGN_1: + case OPC_ALIGN_2: + case OPC_ALIGN_3: case OPC_BITSWAP: check_insn(ctx, ISA_MIPS32R6); decode_opc_special3_r6(env, ctx); @@ -24869,7 +24887,13 @@ static void decode_opc_special3(CPUMIPSState *env,= DisasContext *ctx) op2 =3D MASK_DBSHFL(ctx->opcode); switch (op2) { case OPC_DALIGN: - case OPC_DALIGN_END: + case OPC_DALIGN_1: + case OPC_DALIGN_2: + case OPC_DALIGN_3: + case OPC_DALIGN_4: + case OPC_DALIGN_5: + case OPC_DALIGN_6: + case OPC_DALIGN_7: case OPC_DBITSWAP: check_insn(ctx, ISA_MIPS32R6); decode_opc_special3_r6(env, ctx); --=20 2.7.4