From nobody Thu Nov 6 10:38:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15403894063098.061882642637215; Wed, 24 Oct 2018 06:56:46 -0700 (PDT) Received: from localhost ([::1]:48596 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJeP-0002b4-4H for importer@patchew.org; Wed, 24 Oct 2018 09:56:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJQb-00058k-3s for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFJQZ-0001zl-1o for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:28 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49948 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFJQY-0001rQ-Is for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:26 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C0D9B1A4588; Wed, 24 Oct 2018 15:40:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9EF7D1A4575; Wed, 24 Oct 2018 15:40:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 15:40:32 +0200 Message-Id: <1540388447-27062-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Fredrik Noring Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions. Reviewed-by: Aleksandar Markovic Signed-off-by: Fredrik Noring Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6d89002..d7d7145 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4229,17 +4229,21 @@ static void gen_shift(DisasContext *ctx, uint32_t o= pc, /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D OPC_MFLO)) { + if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D TX79_MMI_MFHI1 = || + opc =3D=3D OPC_MFLO || opc =3D=3D TX79_MMI_MFLO1)) { /* Treat as NOP. */ return; } =20 if (acc !=3D 0) { - check_dsp(ctx); + if (!(ctx->insn_flags & INSN_R5900)) { + check_dsp(ctx); + } } =20 switch (opc) { case OPC_MFHI: + case TX79_MMI_MFHI1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); @@ -4250,6 +4254,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MFLO: + case TX79_MMI_MFLO1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); @@ -4260,6 +4265,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTHI: + case TX79_MMI_MTHI1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -4274,6 +4280,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTLO: + case TX79_MMI_MTLO1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -24658,13 +24665,17 @@ static void decode_tx79_mmi(CPUMIPSState *env, Di= sasContext *ctx) case TX79_MMI_MULTU1: gen_mul_txx9(ctx, opc, rd, rs, rt); break; + case TX79_MMI_MTLO1: + case TX79_MMI_MTHI1: + gen_HILO(ctx, opc, 1, rs); + break; + case TX79_MMI_MFLO1: + case TX79_MMI_MFHI1: + gen_HILO(ctx, opc, 1, rd); + break; case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */ case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */ - case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */ - case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */ - case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */ - case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */ case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */ case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */ case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */ --=20 2.7.4