From nobody Thu Nov 6 10:30:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540388860348762.6658730102486; Wed, 24 Oct 2018 06:47:40 -0700 (PDT) Received: from localhost ([::1]:48552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJVX-00022y-Kv for importer@patchew.org; Wed, 24 Oct 2018 09:47:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFJQK-0004s4-59 for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFJQI-0001pq-EK for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:11 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49893 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFJQG-0001m3-Bz for qemu-devel@nongnu.org; Wed, 24 Oct 2018 09:42:09 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 580C81A456F; Wed, 24 Oct 2018 15:40:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 358DA1A455E; Wed, 24 Oct 2018 15:40:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 15:40:23 +0200 Message-Id: <1540388447-27062-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540388447-27062-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 09/33] target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Fredrik Noring Add placeholder for SQ instruction, handle RDHWR. Reviewed-by: Aleksandar Markovic Signed-off-by: Fredrik Noring Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3c6a2c9..19a8aba 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24420,6 +24420,53 @@ static void decode_opc_special3_legacy(CPUMIPSStat= e *env, DisasContext *ctx) } } =20 +static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset) +{ + generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */ +} + +/* + * The TX79-specific instruction Store Quadword + * + * +--------+-------+-------+------------------------+ + * | 011111 | base | rt | offset | SQ + * +--------+-------+-------+------------------------+ + * 6 5 5 16 + * + * has the same opcode as the Read Hardware Register instruction + * + * +--------+-------+-------+-------+-------+--------+ + * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR + * +--------+-------+-------+-------+-------+--------+ + * 6 5 5 5 5 6 + * + * that is required, trapped and emulated by the Linux kernel. However, all + * RDHWR encodings yield address error exceptions on the TX79 since the SQ + * offset is odd. Therefore all valid SQ instructions can execute normally. + * In user mode, QEMU must verify the upper and lower 11 bits to distingui= sh + * between SQ and RDHWR, as the Linux kernel does. + */ +static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx) +{ + int base =3D extract32(ctx->opcode, 21, 5); + int rt =3D extract32(ctx->opcode, 16, 5); + int offset =3D extract32(ctx->opcode, 0, 16); + +#ifdef CONFIG_USER_ONLY + uint32_t op1 =3D MASK_SPECIAL3(ctx->opcode); + uint32_t op2 =3D extract32(ctx->opcode, 6, 5); + + if (base =3D=3D 0 && op2 =3D=3D 0 && op1 =3D=3D OPC_RDHWR) { + int rd =3D extract32(ctx->opcode, 11, 5); + + gen_rdhwr(ctx, rt, rd, 0); + return; + } +#endif + + gen_tx79_sq(ctx, base, rt, offset); +} + static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -25720,7 +25767,11 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: - decode_opc_special3(env, ctx); + if (ctx->insn_flags & INSN_R5900) { + decode_tx79_sq(env, ctx); /* TX79_SQ */ + } else { + decode_opc_special3(env, ctx); + } break; case OPC_REGIMM: op1 =3D MASK_REGIMM(ctx->opcode); --=20 2.7.4