From nobody Thu Nov 6 10:28:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154038434090469.82718587098896; Wed, 24 Oct 2018 05:32:20 -0700 (PDT) Received: from localhost ([::1]:48148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFIKh-0003hw-T0 for importer@patchew.org; Wed, 24 Oct 2018 08:32:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFIAh-0002Hd-Fr for qemu-devel@nongnu.org; Wed, 24 Oct 2018 08:22:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFIAc-0004Gw-Dz for qemu-devel@nongnu.org; Wed, 24 Oct 2018 08:21:59 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:42282 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFIAc-0004DA-1i for qemu-devel@nongnu.org; Wed, 24 Oct 2018 08:21:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 751B41A4561; Wed, 24 Oct 2018 14:21:50 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id E7E0E1A22AD; Wed, 24 Oct 2018 14:21:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 14:18:47 +0200 Message-Id: <1540383527-7923-21-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540383527-7923-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540383527-7923-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v7 20/20] target/mips: Amend MXU ASE overview note X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add prefix, suffix, operation descriptions, and other corrections and amendments to the comment that describes MXU ASE. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 84 +++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 74 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3620ae5..9bd5f27 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1410,25 +1410,89 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is * the control register. * - * The notation used in MXU assembler mnemonics: + * The notation used in MXU assembler mnemonics + * -------------------------------------------- + * + * Registers: * * XRa, XRb, XRc, XRd - MXU registers * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers - * s12 - a subfield of an instruction code - * strd2 - a subfield of an instruction code - * eptn2 - a subfield of an instruction code - * eptn3 - a subfield of an instruction code - * optn2 - a subfield of an instruction code - * optn3 - a subfield of an instruction code - * sft4 - a subfield of an instruction code + * + * Subfields: + * + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount + * + * Prefixes: + * + * + * S 32 + * D 16 + * Q 8 + * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * Operations: + * + * ADD - Add or subtract + * ADDC - Add with carry-in + * ACC - Accumulate + * ASUM - Sum together then accumulate (add or subtract) + * ASUMC - Sum together then accumulate (add or subtract) with carry-in + * AVG - Average between 2 operands + * ABD - Absolute difference + * ALN - Align data + * AND - Logical bitwise 'and' operation + * CPS - Copy sign + * EXTR - Extract bits + * I2M - Move from GPR register to MXU register + * LDD - Load data from memory to XRF + * LDI - Load data from memory to XRF (and increase the address base) + * LUI - Load unsigned immediate + * MUL - Multiply + * MULU - Unsigned multiply + * MADD - 64-bit operand add 32x32 product + * MSUB - 64-bit operand subtract 32x32 product + * MAC - Multiply and accumulate (add or subtract) + * MAD - Multiply and add or subtract + * MAX - Maximum between 2 operands + * MIN - Minimum between 2 operands + * M2I - Move from MXU register to GPR register + * MOVZ - Move if zero + * MOVN - Move if non-zero + * NOR - Logical bitwise 'nor' operation + * OR - Logical bitwise 'or' operation + * STD - Store data from XRF to memory + * SDI - Store data from XRF to memory (and increase the address base) + * SLT - Set of less than comparison + * SAD - Sum of absolute differences + * SLL - Logical shift left + * SLR - Logical shift right + * SAR - Arithmetic shift right + * SAT - Saturation + * SFL - Shuffle + * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) + * XOR - Logical bitwise 'exclusive or' operation * * Load/Store instructions Multiplication instructions * ----------------------- --------------------------- * * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt - * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt - * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt + * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt + * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 --=20 2.7.4