From nobody Tue Feb 10 12:43:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540311673651753.3724446774229; Tue, 23 Oct 2018 09:21:13 -0700 (PDT) Received: from localhost ([::1]:43222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEzQW-0006g6-TR for importer@patchew.org; Tue, 23 Oct 2018 12:21:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEzOi-0005iZ-G2 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:19:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEzOf-0000ev-5t for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:19:12 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:44758 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gEzOe-0000eZ-Sg for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:19:09 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 940571A44FB; Tue, 23 Oct 2018 18:19:07 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 573C91A21B4; Tue, 23 Oct 2018 18:19:07 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 18:18:12 +0200 Message-Id: <1540311509-23970-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Craig Janeczek Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 10 ++++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e48be4b..03c03fd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,16 @@ struct TCState { MSACSR_FS_MASK) =20 float_status msa_fp_status; + +#define NUMBER_OF_MXU_REGISTERS 16 + target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; + target_ulong mxu_cr; +#define MXU_CR_LC 31 +#define MXU_CR_RC 30 +#define MXU_CR_BIAS 2 +#define MXU_CR_RD_EN 1 +#define MXU_CR_MXU_EN 0 + }; =20 typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index 92df8da..c1f692c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2379,6 +2379,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 +/* MXU registers */ +static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; +static TCGv mxu_CR; + #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -2501,6 +2505,11 @@ static const char * const msaregnames[] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", +}; + #define LOG_DISAS(...) = \ do { = \ if (MIPS_DEBUG_DISAS) { = \ @@ -27091,6 +27100,17 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); + + for (i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); } =20 #include "translate_init.inc.c" --=20 2.7.4