From nobody Thu Nov 6 10:37:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540312369908759.5125695348399; Tue, 23 Oct 2018 09:32:49 -0700 (PDT) Received: from localhost ([::1]:43287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEzbq-0000zL-LW for importer@patchew.org; Tue, 23 Oct 2018 12:32:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEzQA-0006xV-J7 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEzQ9-0001dZ-DZ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46459 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gEzQ8-0001bN-VP for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8800D1A2440; Tue, 23 Oct 2018 18:20:39 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3C8B21A21B4; Tue, 23 Oct 2018 18:20:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 18:18:24 +0200 Message-Id: <1540311509-23970-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Move MUL, S32M2I, S32I2M handling out of switch. These are all instructions that do not depend on MXU_EN flag of MXU_CR. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c8c71c4..111affb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24859,6 +24859,29 @@ static void decode_opc_mxu(CPUMIPSState *env, Disa= sContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 0, 6); =20 + if (opcode =3D=3D OPC__MXU_MUL) { + uint32_t rs, rt, rd, op1; + + rs =3D extract32(ctx->opcode, 21, 5); + rt =3D extract32(ctx->opcode, 16, 5); + rd =3D extract32(ctx->opcode, 11, 5); + op1 =3D MASK_SPECIAL2(ctx->opcode); + + gen_arith(ctx, op1, rd, rs, rt); + + return; + } + + if (opcode =3D=3D OPC_MXU_S32M2I) { + gen_mxu_s32m2i(ctx); + return; + } + + if (opcode =3D=3D OPC_MXU_S32I2M) { + gen_mxu_s32i2m(ctx); + return; + } + switch (opcode) { case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ @@ -24870,18 +24893,6 @@ static void decode_opc_mxu(CPUMIPSState *env, Disa= sContext *ctx) MIPS_INVAL("OPC_MXU_S32MADDU"); generate_exception_end(ctx, EXCP_RI); break; - case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */ - { - uint32_t rs, rt, rd, op1; - - rs =3D extract32(ctx->opcode, 21, 5); - rt =3D extract32(ctx->opcode, 16, 5); - rd =3D extract32(ctx->opcode, 11, 5); - op1 =3D MASK_SPECIAL2(ctx->opcode); - - gen_arith(ctx, op1, rd, rs, rt); - } - break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; @@ -25033,12 +25044,6 @@ static void decode_opc_mxu(CPUMIPSState *env, Disa= sContext *ctx) MIPS_INVAL("OPC_MXU_S16SDI"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU_S32M2I: - gen_mxu_s32m2i(ctx); - break; - case OPC_MXU_S32I2M: - gen_mxu_s32i2m(ctx); - break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); --=20 2.7.4