From nobody Thu Nov 6 10:36:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540312501847256.5638968511389; Tue, 23 Oct 2018 09:35:01 -0700 (PDT) Received: from localhost ([::1]:43293 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEze0-0002Qh-KB for importer@patchew.org; Tue, 23 Oct 2018 12:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEzQ9-0006w3-4L for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEzQ7-0001aY-DP for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:40 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46219 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gEzQ6-0001Vb-Pm for qemu-devel@nongnu.org; Tue, 23 Oct 2018 12:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3D85E1A44FF; Tue, 23 Oct 2018 18:20:33 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id E9B601A21B4; Tue, 23 Oct 2018 18:20:32 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 18:18:23 +0200 Message-Id: <1540311509-23970-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 12/18] target/mips: Add emulation of MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Craig Janeczek Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 29df4ce..c8c71c4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2575,6 +2575,35 @@ static inline void gen_store_srsgpr (int from, int t= o) } } =20 +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <=3D 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <=3D 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(mxu_CR, t); +} + + /* Tests */ static inline void gen_save_pc(target_ulong pc) { @@ -23879,6 +23908,59 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) =20 =20 /* + * S32I2M XRa, rb - Register move from GRF to XRF + */ +static void gen_mxu_s32i2m(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, Rb); + if (XRa <=3D 15) { + gen_store_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* + * S32M2I XRa, rb - Register move from XRF to GRF + */ +static void gen_mxu_s32m2i(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + if (XRa <=3D 15) { + gen_load_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, Rb); + + tcg_temp_free(t0); +} + + +/* + * Decoding engine for MXU + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + */ + +/* * * Decode MXU pool00 * @@ -24952,14 +25034,10 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32M2I: - /* TODO: Implement emulation of S32M2I instruction. */ - MIPS_INVAL("OPC_MXU_S32M2I"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32m2i(ctx); break; case OPC_MXU_S32I2M: - /* TODO: Implement emulation of S32I2M instruction. */ - MIPS_INVAL("OPC_MXU_S32I2M"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32i2m(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ --=20 2.7.4