From nobody Tue Feb 10 07:42:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539889223374148.46501301645287; Thu, 18 Oct 2018 12:00:23 -0700 (PDT) Received: from localhost ([::1]:43948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDDWw-0003EV-7H for importer@patchew.org; Thu, 18 Oct 2018 15:00:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDDMX-0000n3-Ea for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:49:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDDMW-0005pO-JY for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:49:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56956 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDDMW-0005em-BY for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:49:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C8B661A416F; Thu, 18 Oct 2018 20:48:03 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 98B891A4158; Thu, 18 Oct 2018 20:48:03 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 20:47:41 +0200 Message-Id: <1539888473-16340-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539888473-16340-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539888473-16340-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 16/28] target/mips: Add bit definitions for DSP R3 ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add DSP R3 ASE related bit definition for insn_flags and hflags. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/mips-defs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3b3509c..7f4e6d0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -795,6 +795,7 @@ struct CPUMIPSState { /* MIPS DSP resources access. */ #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources.= */ #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resource= s. */ +#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resourc= es.*/ /* Extra flag about HWREna register. */ #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mod= e */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 66b7953..a23c4ed 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -53,6 +53,7 @@ #define ASE_MDMX 0x0000000400000000ULL #define ASE_DSP 0x0000000800000000ULL #define ASE_DSPR2 0x0000001000000000ULL +#define ASE_DSPR3 0x0000002000000000ULL #define ASE_MT 0x0000004000000000ULL #define ASE_SMARTMIPS 0x0000008000000000ULL #define ASE_MICROMIPS 0x0000010000000000ULL --=20 2.7.4