From nobody Thu Nov 6 08:24:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539780560277402.7204406693471; Wed, 17 Oct 2018 05:49:20 -0700 (PDT) Received: from localhost ([::1]:36459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gClGJ-0005QP-4w for importer@patchew.org; Wed, 17 Oct 2018 08:49:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCl2w-0001z3-1c for qemu-devel@nongnu.org; Wed, 17 Oct 2018 08:35:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCl2t-0006uk-48 for qemu-devel@nongnu.org; Wed, 17 Oct 2018 08:35:29 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39443 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCl2s-0006ep-Bd for qemu-devel@nongnu.org; Wed, 17 Oct 2018 08:35:26 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1CD9E1A2162; Wed, 17 Oct 2018 14:34:07 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D78B61A209F; Wed, 17 Oct 2018 14:34:06 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 17 Oct 2018 14:33:40 +0200 Message-Id: <1539779635-15445-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539779635-15445-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539779635-15445-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add opcode values for all instructions in MXU ASE. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 276 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 276 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 45ed1d9..4d652dc 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1652,6 +1652,282 @@ enum { * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 */ =20 +enum { + OPC_MXU_S32MADD =3D 0x00, + OPC_MXU_S32MADDU =3D 0x01, + /* not assigned 0x02 */ + OPC_MXU__POOL00 =3D 0x03, + OPC_MXU_S32MSUB =3D 0x04, + OPC_MXU_S32MSUBU =3D 0x05, + OPC_MXU__POOL01 =3D 0x06, + OPC_MXU__POOL02 =3D 0x07, + OPC_MXU_D16MUL =3D 0x08, + OPC_MXU__POOL03 =3D 0x09, + OPC_MXU_D16MAC =3D 0x0A, + OPC_MXU_D16MACF =3D 0x0B, + OPC_MXU_D16MADL =3D 0x0C, + OPC_MXU__POOL04 =3D 0x0D, + OPC_MXU_Q16ADD =3D 0x0E, + OPC_MXU_D16MACE =3D 0x0F, + OPC_MXU__POOL05 =3D 0x10, + OPC_MXU__POOL06 =3D 0x11, + OPC_MXU__POOL07 =3D 0x12, + OPC_MXU__POOL08 =3D 0x13, + OPC_MXU__POOL09 =3D 0x14, + OPC_MXU__POOL10 =3D 0x15, + OPC_MXU__POOL11 =3D 0x16, + OPC_MXU__POOL12 =3D 0x17, + OPC_MXU_D32ADD =3D 0x18, + OPC_MXU__POOL13 =3D 0x19, + /* not assigned 0x1A */ + OPC_MXU__POOL14 =3D 0x1B, + OPC_MXU__POOL15 =3D 0x1C, + OPC_MXU_Q8ACCE =3D 0x1D, + /* not assigned 0x1E */ + /* not assigned 0x1F */ + /* not assigned 0x20 */ + /* not assigned 0x21 */ + OPC_MXU_S8LDD =3D 0x22, + OPC_MXU_S8STD =3D 0x23, + OPC_MXU_S8LDI =3D 0x24, + OPC_MXU_S8SDI =3D 0x25, + OPC_MXU__POOL16 =3D 0x26, + OPC_MXU__POOL17 =3D 0x27, + OPC_MXU_LXB =3D 0x28, + /* not assigned 0x29 */ + OPC_MXU_S16LDD =3D 0x2A, + OPC_MXU_S16STD =3D 0x2B, + OPC_MXU_S16LDI =3D 0x2C, + OPC_MXU_S16SDI =3D 0x2D, + OPC_MXU_S32M2I =3D 0x2E, + OPC_MXU_S32I2M =3D 0x2F, + OPC_MXU_D32SLL =3D 0x30, + OPC_MXU_D32SLR =3D 0x31, + OPC_MXU_D32SARL =3D 0x32, + OPC_MXU_D32SAR =3D 0x33, + OPC_MXU_Q16SLL =3D 0x34, + OPC_MXU_Q16SLR =3D 0x35, + OPC_MXU__POOL18 =3D 0x36, + OPC_MXU_Q16SAR =3D 0x37, + OPC_MXU__POOL19 =3D 0x38, + OPC_MXU__POOL20 =3D 0x39, + OPC_MXU__POOL21 =3D 0x3A, + OPC_MXU_Q16SCOP =3D 0x3B, + OPC_MXU_Q8MADL =3D 0x3C, + OPC_MXU_S32SFL =3D 0x3D, + OPC_MXU_Q8SAD =3D 0x3E, + /* not assigned 0x3F */ +}; + + +/* + * MXU pool 00 + */ +enum { + OPC_MXU_S32MAX =3D 0x00, + OPC_MXU_S32MIN =3D 0x01, + OPC_MXU_D16MAX =3D 0x02, + OPC_MXU_D16MIN =3D 0x03, + OPC_MXU_Q8MAX =3D 0x04, + OPC_MXU_Q8MIN =3D 0x05, + OPC_MXU_Q8SLT =3D 0x06, + OPC_MXU_Q8SLTU =3D 0x07, +}; + +/* + * MXU pool 01 + */ +enum { + OPC_MXU_S32SLT =3D 0x00, + OPC_MXU_D16SLT =3D 0x01, + OPC_MXU_D16AVG =3D 0x02, + OPC_MXU_D16AVGR =3D 0x03, + OPC_MXU_Q8AVG =3D 0x04, + OPC_MXU_Q8AVGR =3D 0x05, + OPC_MXU_Q8ADD =3D 0x07, +}; + +/* + * MXU pool 02 + */ +enum { + OPC_MXU_S32CPS =3D 0x00, + OPC_MXU_D16CPS =3D 0x02, + OPC_MXU_Q8ABD =3D 0x04, + OPC_MXU_Q16SAT =3D 0x06, +}; + +/* + * MXU pool 03 + */ +enum { + OPC_MXU_D16MULF =3D 0x00, + OPC_MXU_D16MULE =3D 0x01, +}; + +/* + * MXU pool 04 + */ +enum { + OPC_MXU_S16MAD =3D 0x00, + OPC_MXU_S16MAD_1 =3D 0x01, +}; + +/* + * MXU pool 05 + */ +enum { + OPC_MXU_S32LDD =3D 0x00, + OPC_MXU_S32LDDR =3D 0x01, +}; + +/* + * MXU pool 06 + */ +enum { + OPC_MXU_S32STD =3D 0x00, + OPC_MXU_S32STDR =3D 0x01, +}; + +/* + * MXU pool 07 + */ +enum { + OPC_MXU_S32LDDV =3D 0x00, + OPC_MXU_S32LDDVR =3D 0x01, +}; + +/* + * MXU pool 08 + */ +enum { + OPC_MXU_S32TDV =3D 0x00, + OPC_MXU_S32TDVR =3D 0x01, +}; + +/* + * MXU pool 09 + */ +enum { + OPC_MXU_S32LDI =3D 0x00, + OPC_MXU_S32LDIR =3D 0x01, +}; + +/* + * MXU pool 10 + */ +enum { + OPC_MXU_S32SDI =3D 0x00, + OPC_MXU_S32SDIR =3D 0x01, +}; + +/* + * MXU pool 11 + */ +enum { + OPC_MXU_S32LDIV =3D 0x00, + OPC_MXU_S32LDIVR =3D 0x01, +}; + +/* + * MXU pool 12 + */ +enum { + OPC_MXU_S32SDIV =3D 0x00, + OPC_MXU_S32SDIVR =3D 0x01, +}; + +/* + * MXU pool 13 + */ +enum { + OPC_MXU_D32ACC =3D 0x00, + OPC_MXU_D32ACCM =3D 0x01, + OPC_MXU_D32ASUM =3D 0x02, +}; + +/* + * MXU pool 14 + */ +enum { + OPC_MXU_Q16ACC =3D 0x00, + OPC_MXU_Q16ACCM =3D 0x01, + OPC_MXU_Q16ASUM =3D 0x02, +}; + +/* + * MXU pool 15 + */ +enum { + OPC_MXU_Q8ADDE =3D 0x00, + OPC_MXU_D8SUM =3D 0x01, + OPC_MXU_D8SUMC =3D 0x02, +}; + +/* + * MXU pool 16 + */ +enum { + OPC_MXU_S32MUL =3D 0x00, + OPC_MXU_S32MULU =3D 0x01, + OPC_MXU_S32EXTR =3D 0x02, + OPC_MXU_S32EXTRV =3D 0x03, +}; + +/* + * MXU pool 17 + */ +enum { + OPC_MXU_D32SARW =3D 0x00, + OPC_MXU_S32ALN =3D 0x01, + OPC_MXU_S32ALNI =3D 0x02, + OPC_MXU_S32NOR =3D 0x03, + OPC_MXU_S32AND =3D 0x04, + OPC_MXU_S32OR =3D 0x05, + OPC_MXU_S32XOR =3D 0x06, + OPC_MXU_S32LUI =3D 0x07, +}; + +/* + * MXU pool 18 + */ +enum { + OPC_MXU_D32SLLV =3D 0x00, + OPC_MXU_D32SLRV =3D 0x01, + OPC_MXU_D32SARV =3D 0x03, + OPC_MXU_Q16SLLV =3D 0x04, + OPC_MXU_Q16SLRV =3D 0x05, + OPC_MXU_Q16SARV =3D 0x07, +}; + +/* + * MXU pool 19 + */ +enum { + OPC_MXU_Q8MUL =3D 0x00, + OPC_MXU_Q8MULSU =3D 0x01, +}; + +/* + * MXU pool 20 + */ +enum { + OPC_MXU_Q8MOVZ =3D 0x00, + OPC_MXU_Q8MOVN =3D 0x01, + OPC_MXU_D16MOVZ =3D 0x02, + OPC_MXU_D16MOVN =3D 0x03, + OPC_MXU_S32MOVZ =3D 0x04, + OPC_MXU_S32MOVN =3D 0x05, +}; + +/* + * MXU pool 21 + */ +enum { + OPC_MXU_Q8MAC =3D 0x00, + OPC_MXU_Q8MACSU =3D 0x01, +}; + =20 /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; --=20 2.7.4