From nobody Thu Nov 6 06:17:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539692379929718.0444111709633; Tue, 16 Oct 2018 05:19:39 -0700 (PDT) Received: from localhost ([::1]:57725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOK2-0007Le-IX for importer@patchew.org; Tue, 16 Oct 2018 08:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59081) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOG7-0004Kh-Cj for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCOG1-0007yB-An for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:35 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38924 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCOFz-00079J-AI for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:29 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CAE761A2147; Tue, 16 Oct 2018 14:14:20 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id AFDD91A1EA3; Tue, 16 Oct 2018 14:14:20 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 14:14:01 +0200 Message-Id: <1539692044-15732-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, amarkovic@wavecomp.com, jancraig@amazon.com, aurelien@aurel32.net, pjovanovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add a comment that contains a basic description of MXU ASE. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb..23e21c5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1389,6 +1389,26 @@ enum { OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, }; =20 + +/* + * AN OVERVIEW OF MXU EXTENSTION INSTRUCTION SET + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of M= IPS32 + * instructions set. It is designed to fit the needs of signal, graphical = and + * video processing applications. MXU instruction set is used in Xburst fa= mily + * of microprocessors by Ingenic. + * + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is + * the control register. + * + * Compiled after: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + */ + + /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; --=20 2.7.4