From nobody Thu Nov 6 03:30:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539692379929718.0444111709633; Tue, 16 Oct 2018 05:19:39 -0700 (PDT) Received: from localhost ([::1]:57725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOK2-0007Le-IX for importer@patchew.org; Tue, 16 Oct 2018 08:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59081) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOG7-0004Kh-Cj for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCOG1-0007yB-An for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:35 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38924 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCOFz-00079J-AI for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:29 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CAE761A2147; Tue, 16 Oct 2018 14:14:20 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id AFDD91A1EA3; Tue, 16 Oct 2018 14:14:20 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 14:14:01 +0200 Message-Id: <1539692044-15732-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, amarkovic@wavecomp.com, jancraig@amazon.com, aurelien@aurel32.net, pjovanovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add a comment that contains a basic description of MXU ASE. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb..23e21c5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1389,6 +1389,26 @@ enum { OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, }; =20 + +/* + * AN OVERVIEW OF MXU EXTENSTION INSTRUCTION SET + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of M= IPS32 + * instructions set. It is designed to fit the needs of signal, graphical = and + * video processing applications. MXU instruction set is used in Xburst fa= mily + * of microprocessors by Ingenic. + * + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is + * the control register. + * + * Compiled after: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + */ + + /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; --=20 2.7.4 From nobody Thu Nov 6 03:30:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539692267545313.36621837507744; Tue, 16 Oct 2018 05:17:47 -0700 (PDT) Received: from localhost ([::1]:57715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOIE-0005UA-8Y for importer@patchew.org; Tue, 16 Oct 2018 08:17:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOG7-0004Kf-Cg for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCOG5-00082U-AW for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:35 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39173 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCOG3-0007GP-AV for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 040611A21F1; Tue, 16 Oct 2018 14:14:27 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DCC3B1A223E; Tue, 16 Oct 2018 14:14:26 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 14:14:02 +0200 Message-Id: <1539692044-15732-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, amarkovic@wavecomp.com, jancraig@amazon.com, aurelien@aurel32.net, pjovanovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add a comment that contains a list all MXU instructions, expressed in assembler mnemonics. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 88 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 23e21c5..73d971e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1402,6 +1402,94 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is * the control register. * + * The notation used in MXU assembler mnemonics: + * + * XRa, XRb, XRa, XRb - MXU registers + * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers + * s12 - a subfield of an instruction code + * strd2 - a subfield of an instruction code + * eptn2 - a subfield of an instruction code + * eptn3 - a subfield of an instruction code + * optn2 - a subfield of an instruction code + * optn3 - a subfield of an instruction code + * sft4 - a subfield of an instruction code + * + * Load/Store instructions Multiplication instructions + * ----------------------- --------------------------- + * + * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt + * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt + * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt + * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt + * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt + * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt + * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 + * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2 + * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2 + * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, op= tn2 + * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, op= tn2 + * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd + * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd + * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2 + * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2 + * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2 + * S16SDI XRa, Rb, s10, eptn2 + * S8LDD XRa, Rb, s8, eptn3 + * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions + * S8LDI XRa, Rb, s8, eptn3 ------------------------------------- + * S8SDI XRa, Rb, s8, eptn3 + * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2 + * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd + * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2 + * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2 + * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2 + * S32CPS XRa, XRb, XRc + * Q16ADD XRa, XRb, XRc, XRd, eptn2, op= tn2 + * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2 + * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2 + * D16ASUM XRa, XRb, XRc, XRd, eptn2 + * S32MAX XRa, XRb, XRc D16CPS XRa, XRb, + * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc + * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc + * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2 + * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2 + * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2 + * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc + * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd + * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc + * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc + * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd + * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd + * Q8SLT XRa, XRb, XRc + * Q8SLTU XRa, XRb, XRc + * Q8MOVZ XRa, XRb, XRc Shift instructions + * Q8MOVN XRa, XRb, XRc ------------------ + * + * D32SLL XRa, XRb, XRc, XRd, sft4 + * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4 + * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4 + * D32SARL XRa, XRb, XRc, sft4 + * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb + * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb + * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb + * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb + * Q16SLL XRa, XRb, XRc, XRd, sft4 + * Q16SLR XRa, XRb, XRc, XRd, sft4 + * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 + * ------------------------- Q16SLLV XRa, XRb, Rb + * Q16SLRV XRa, XRb, Rb + * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb + * S32ALN XRa, XRb, XRc, Rb + * S32ALNI XRa, XRb, XRc, s3 + * S32LUI XRa, s8, optn3 Move instructions + * S32EXTR XRa, XRb, Rb, bits5 ----------------- + * S32EXTRV XRa, XRb, Rs, Rt + * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb + * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb + * * Compiled after: * * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it --=20 2.7.4 From nobody Thu Nov 6 03:30:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539692400343406.11676493321465; Tue, 16 Oct 2018 05:20:00 -0700 (PDT) Received: from localhost ([::1]:57727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOKN-0007bH-68 for importer@patchew.org; Tue, 16 Oct 2018 08:19:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59128) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOG8-0004Lo-ST for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCOG7-00085n-F2 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39287 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCOG6-0007JO-9j for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9302D1A215D; Tue, 16 Oct 2018 14:14:30 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 753201A2149; Tue, 16 Oct 2018 14:14:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 14:14:03 +0200 Message-Id: <1539692044-15732-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, amarkovic@wavecomp.com, jancraig@amazon.com, aurelien@aurel32.net, pjovanovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add a comment that contains an organizational chart of MXU ASE instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 156 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 73d971e..4dfc360 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1490,6 +1490,162 @@ enum { * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb * + * + * bits + * 05..00 + * + * =E2=94=8C=E2=94=80 000000 =E2=94=80 OPC_MXU_S32MADD + * =E2=94=9C=E2=94=80 000001 =E2=94=80 OPC_MXU_S32MADDU + * =E2=94=9C=E2=94=80 000010 =E2=94=80 + * =E2=94=82 20..18 (25..21 must b= e 0) + * =E2=94=9C=E2=94=80 000011 =E2=94=80 OPC_MXU__POOL00 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32MAX + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32MIN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MAX + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MIN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8MAX + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8MIN + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_Q8SLT + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8SLTU + * =E2=94=9C=E2=94=80 000100 =E2=94=80 OPC_MXU_S32MSUB + * =E2=94=9C=E2=94=80 000101 =E2=94=80 OPC_MXU_S32MSUBU 20..18= (25..21 must be 0, + * =E2=94=82 except for Q= 8ADD) + * =E2=94=9C=E2=94=80 000110 =E2=94=80 OPC_MXU__POOL01 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32SLT + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D16SLT + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16AVG + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16AVGR + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8AVG + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8AVGR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8ADD + * =E2=94=82 + * =E2=94=82 20..18 (25..21 must b= e 0) + * =E2=94=9C=E2=94=80 000111 =E2=94=80 OPC_MXU__POOL02 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32CPS + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16CPS + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8ABD + * =E2=94=82 =E2=94=94=E2=94=80 110 = =E2=94=80 OPC_MXU_Q16SAT + * =E2=94=9C=E2=94=80 001000 =E2=94=80 OPC_MXU_D16MUL + * =E2=94=82 25..24 + * =E2=94=9C=E2=94=80 001001 =E2=94=80 OPC_MXU__POOL03 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D16MULF + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_D16MULE + * =E2=94=9C=E2=94=80 001010 =E2=94=80 OPC_MXU_D16MAC + * =E2=94=9C=E2=94=80 001011 =E2=94=80 OPC_MXU_D16MACF + * =E2=94=9C=E2=94=80 001100 =E2=94=80 OPC_MXU_D16MADL + * =E2=94=82 25..24 + * =E2=94=9C=E2=94=80 001101 =E2=94=80 OPC_MXU__POOL04 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_S16MAD + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_S16MAD_1 + * =E2=94=9C=E2=94=80 001110 =E2=94=80 OPC_MXU_Q16ADD + * =E2=94=9C=E2=94=80 001111 =E2=94=80 OPC_MXU_D16MACE + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010000 =E2=94=80 OPC_MXU__POOL05 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDD + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDDR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010001 =E2=94=80 OPC_MXU__POOL06 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32STD + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32STDR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010010 =E2=94=80 OPC_MXU__POOL07 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDDVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010011 =E2=94=80 OPC_MXU__POOL08 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32TDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32TDVR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010100 =E2=94=80 OPC_MXU__POOL09 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDIR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010101 =E2=94=80 OPC_MXU__POOL10 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32SDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32SDIR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010110 =E2=94=80 OPC_MXU__POOL11 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDIVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010111 =E2=94=80 OPC_MXU__POOL12 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32SDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32SDIVR + * =E2=94=9C=E2=94=80 011000 =E2=94=80 OPC_MXU_D32ADD + * =E2=94=82 + * MXU =E2=94=9C=E2=94=80 011001 =E2=94=80 OPC_MXU__POOL13 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D32ACC + * opcodes =E2=94=80=E2=94=A4 =E2=94=9C=E2=94= =80 01 =E2=94=80 OPC_MXU_D32ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_D32ASUM + * =E2=94=9C=E2=94=80 011010 =E2=94=80 + * =E2=94=82 + * =E2=94=9C=E2=94=80 011011 =E2=94=80 OPC_MXU__POOL14 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q16ACC + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_Q16ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q16ASUM + * =E2=94=82 + * =E2=94=82 + * =E2=94=9C=E2=94=80 011100 =E2=94=80 OPC_MXU__POOL15 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8ADDE + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_D8SUM + * =E2=94=9C=E2=94=80 011101 =E2=94=80 OPC_MXU_Q8ACCE =E2=94=94= =E2=94=80 10 =E2=94=80 OPC_MXU_D8SUMC + * =E2=94=9C=E2=94=80 011110 =E2=94=80 + * =E2=94=9C=E2=94=80 011111 =E2=94=80 + * =E2=94=9C=E2=94=80 100000 =E2=94=80 + * =E2=94=9C=E2=94=80 100001 =E2=94=80 + * =E2=94=9C=E2=94=80 100010 =E2=94=80 OPC_MXU_S8LDD + * =E2=94=9C=E2=94=80 100011 =E2=94=80 OPC_MXU_S8STD + * =E2=94=9C=E2=94=80 100100 =E2=94=80 OPC_MXU_S8LDI + * =E2=94=9C=E2=94=80 100101 =E2=94=80 OPC_MXU_S8SDI + * =E2=94=82 + * =E2=94=9C=E2=94=80 100110 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_S32MUL + * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32MULU + * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTR + * =E2=94=82 =E2=94=94=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTRV + * =E2=94=82 + * =E2=94=82 + * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN + * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU_LXB =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_S32ALNI + * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_S32NOR + * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_S32AND + * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=9C= =E2=94=80 101 =E2=94=80 OPC_MXU_S32OR + * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI =E2=94=9C= =E2=94=80 110 =E2=94=80 OPC_MXU_S32XOR + * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI =E2=94=94= =E2=94=80 111 =E2=94=80 OPC_MXU_S32LUI + * =E2=94=9C=E2=94=80 101000 =E2=94=80 + * =E2=94=9C=E2=94=80 101001 =E2=94=80 + * =E2=94=9C=E2=94=80 101010 =E2=94=80 + * =E2=94=9C=E2=94=80 101011 =E2=94=80 + * =E2=94=9C=E2=94=80 101100 =E2=94=80 + * =E2=94=9C=E2=94=80 101101 =E2=94=80 + * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I + * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M + * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL + * =E2=94=9C=E2=94=80 110001 =E2=94=80 OPC_MXU_D32SLR + * =E2=94=9C=E2=94=80 110010 =E2=94=80 OPC_MXU_D32SARL + * =E2=94=9C=E2=94=80 110011 =E2=94=80 OPC_MXU_D32SAR + * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL + * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR + * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SLLV + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D32SLRV + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D32SARV + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_Q16SLLV + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV + * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_Q16SARV + * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR + * =E2=94=82 + * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU + * =E2=94=82 + * =E2=94=82 + * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ + * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOV + * =E2=94=82 + * =E2=94=82 + * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU + * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP + * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL + * =E2=94=9C=E2=94=80 111101 =E2=94=80 OPC_MXU_S32SFL + * =E2=94=9C=E2=94=80 111110 =E2=94=80 OPC_MXU_Q8SAD + * =E2=94=94=E2=94=80 111111 =E2=94=80 + * + * * Compiled after: * * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it --=20 2.7.4 From nobody Thu Nov 6 03:30:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539692270226969.3767689264586; Tue, 16 Oct 2018 05:17:50 -0700 (PDT) Received: from localhost ([::1]:57716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOIH-0005Wr-3a for importer@patchew.org; Tue, 16 Oct 2018 08:17:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCOG9-0004M5-6n for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCOG7-00086K-ST for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39344 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCOG7-0007L4-AL for qemu-devel@nongnu.org; Tue, 16 Oct 2018 08:15:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C41F11A215B; Tue, 16 Oct 2018 14:14:32 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A80EE1A1EA3; Tue, 16 Oct 2018 14:14:32 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 14:14:04 +0200 Message-Id: <1539692044-15732-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539692044-15732-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values of MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, amarkovic@wavecomp.com, jancraig@amazon.com, aurelien@aurel32.net, pjovanovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add opcode values for all instructions in MXU ASE. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 276 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 276 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4dfc360..941b546 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1652,6 +1652,282 @@ enum { * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 */ =20 +enum { + OPC_MXU_S32MADD =3D 0x00, + OPC_MXU_S32MADDU =3D 0x01, + /* not assigned 0x02 */ + OPC_MXU__POOL00 =3D 0x03, + OPC_MXU_S32MSUB =3D 0x04, + OPC_MXU_S32MSUBU =3D 0x05, + OPC_MXU__POOL01 =3D 0x06, + OPC_MXU__POOL02 =3D 0x07, + OPC_MXU_D16MUL =3D 0x08, + OPC_MXU__POOL03 =3D 0x09, + OPC_MXU_D16MAC =3D 0x0A, + OPC_MXU_D16MACF =3D 0x0B, + OPC_MXU_D16MADL =3D 0x0C, + OPC_MXU__POOL04 =3D 0x0D, + OPC_MXU_Q16ADD =3D 0x0E, + OPC_MXU_D16MACE =3D 0x0F, + OPC_MXU__POOL05 =3D 0x10, + OPC_MXU__POOL06 =3D 0x11, + OPC_MXU__POOL07 =3D 0x12, + OPC_MXU__POOL08 =3D 0x13, + OPC_MXU__POOL09 =3D 0x14, + OPC_MXU__POOL10 =3D 0x15, + OPC_MXU__POOL11 =3D 0x16, + OPC_MXU__POOL12 =3D 0x17, + OPC_MXU_D32ADD =3D 0x18, + OPC_MXU__POOL13 =3D 0x19, + /* not assigned 0x1A */ + OPC_MXU__POOL14 =3D 0x1B, + OPC_MXU__POOL15 =3D 0x1C, + OPC_MXU_Q8ACCE =3D 0x1D, + /* not assigned 0x1E */ + /* not assigned 0x1F */ + /* not assigned 0x20 */ + /* not assigned 0x21 */ + OPC_MXU_S8LDD =3D 0x22, + OPC_MXU_S8STD =3D 0x23, + OPC_MXU_S8LDI =3D 0x24, + OPC_MXU_S8SDI =3D 0x25, + OPC_MXU__POOL16 =3D 0x26, + OPC_MXU__POOL17 =3D 0x27, + OPC_MXU_LXB =3D 0x28, + /* not assigned 0x29 */ + OPC_MXU_S16LDD =3D 0x2A, + OPC_MXU_S16STD =3D 0x2B, + OPC_MXU_S16LDI =3D 0x2C, + OPC_MXU_S16SDI =3D 0x2D, + OPC_MXU_S32M2I =3D 0x2E, + OPC_MXU_S32I2M =3D 0x2F, + OPC_MXU_D32SLL =3D 0x30, + OPC_MXU_D32SLR =3D 0x31, + OPC_MXU_D32SARL =3D 0x32, + OPC_MXU_D32SAR =3D 0x33, + OPC_MXU_Q16SLL =3D 0x34, + OPC_MXU_Q16SLR =3D 0x35, + OPC_MXU__POOL18 =3D 0x36, + OPC_MXU_Q16SAR =3D 0x37, + OPC_MXU__POOL19 =3D 0x38, + OPC_MXU__POOL20 =3D 0x39, + OPC_MXU__POOL21 =3D 0x3A, + OPC_MXU_Q16SCOP =3D 0x3B, + OPC_MXU_Q8MADL =3D 0x3C, + OPC_MXU_S32SFL =3D 0x3D, + OPC_MXU_Q8SAD =3D 0x3E, + /* not assigned 0x3F */ +}; + + +/* + * MXU pool 00 + */ +enum { + OPC_MXU_S32MAX =3D 0x00, + OPC_MXU_S32MIN =3D 0x01, + OPC_MXU_D16MAX =3D 0x02, + OPC_MXU_D16MIN =3D 0x03, + OPC_MXU_Q8MAX =3D 0x04, + OPC_MXU_Q8MIN =3D 0x05, + OPC_MXU_Q8SLT =3D 0x06, + OPC_MXU_Q8SLTU =3D 0x07, +}; + +/* + * MXU pool 01 + */ +enum { + OPC_MXU_S32SLT =3D 0x00, + OPC_MXU_D16SLT =3D 0x01, + OPC_MXU_D16AVG =3D 0x02, + OPC_MXU_D16AVGR =3D 0x03, + OPC_MXU_Q8AVG =3D 0x04, + OPC_MXU_Q8AVGR =3D 0x05, + OPC_MXU_Q8ADD =3D 0x07, +}; + +/* + * MXU pool 02 + */ +enum { + OPC_MXU_S32CPS =3D 0x00, + OPC_MXU_D16CPS =3D 0x02, + OPC_MXU_Q8ABD =3D 0x04, + OPC_MXU_Q16SAT =3D 0x06, +}; + +/* + * MXU pool 03 + */ +enum { + OPC_MXU_D16MULF =3D 0x00, + OPC_MXU_D16MULE =3D 0x01, +}; + +/* + * MXU pool 04 + */ +enum { + OPC_MXU_S16MAD =3D 0x00, + OPC_MXU_S16MAD_1 =3D 0x01, +}; + +/* + * MXU pool 05 + */ +enum { + OPC_MXU_S32LDD =3D 0x00, + OPC_MXU_S32LDDR =3D 0x01, +}; + +/* + * MXU pool 06 + */ +enum { + OPC_MXU_S32STD =3D 0x00, + OPC_MXU_S32STDR =3D 0x01, +}; + +/* + * MXU pool 07 + */ +enum { + OPC_MXU_S32LDDV =3D 0x00, + OPC_MXU_S32LDDVR =3D 0x01, +}; + +/* + * MXU pool 08 + */ +enum { + OPC_MXU_S32TDV =3D 0x00, + OPC_MXU_S32TDVR =3D 0x01, +}; + +/* + * MXU pool 09 + */ +enum { + OPC_MXU_S32LDI =3D 0x00, + OPC_MXU_S32LDIR =3D 0x01, +}; + +/* + * MXU pool 10 + */ +enum { + OPC_MXU_S32SDI =3D 0x00, + OPC_MXU_S32SDIR =3D 0x01, +}; + +/* + * MXU pool 11 + */ +enum { + OPC_MXU_S32LDIV =3D 0x00, + OPC_MXU_S32LDIVR =3D 0x01, +}; + +/* + * MXU pool 12 + */ +enum { + OPC_MXU_S32SDIV =3D 0x00, + OPC_MXU_S32SDIVR =3D 0x01, +}; + +/* + * MXU pool 13 + */ +enum { + OPC_MXU_D32ACC =3D 0x00, + OPC_MXU_D32ACCM =3D 0x01, + OPC_MXU_D32ASUM =3D 0x02, +}; + +/* + * MXU pool 14 + */ +enum { + OPC_MXU_Q16ACC =3D 0x00, + OPC_MXU_Q16ACCM =3D 0x01, + OPC_MXU_Q16ASUM =3D 0x02, +}; + +/* + * MXU pool 15 + */ +enum { + OPC_MXU_Q8ADDE =3D 0x00, + OPC_MXU_D8SUM =3D 0x01, + OPC_MXU_D8SUMC =3D 0x02, +}; + +/* + * MXU pool 16 + */ +enum { + OPC_MXU_S32MUL =3D 0x00, + OPC_MXU_S32MULU =3D 0x01, + OPC_MXU_S32EXTR =3D 0x02, + OPC_MXU_S32EXTRV =3D 0x03, +}; + +/* + * MXU pool 17 + */ +enum { + OPC_MXU_D32SARW =3D 0x00, + OPC_MXU_S32ALN =3D 0x01, + OPC_MXU_S32ALNI =3D 0x02, + OPC_MXU_S32NOR =3D 0x03, + OPC_MXU_S32AND =3D 0x04, + OPC_MXU_S32OR =3D 0x05, + OPC_MXU_S32XOR =3D 0x06, + OPC_MXU_S32LUI =3D 0x07, +}; + +/* + * MXU pool 18 + */ +enum { + OPC_MXU_D32SLLV =3D 0x00, + OPC_MXU_D32SLRV =3D 0x01, + OPC_MXU_D32SARV =3D 0x03, + OPC_MXU_Q16SLLV =3D 0x04, + OPC_MXU_Q16SLRV =3D 0x05, + OPC_MXU_Q16SARV =3D 0x07, +}; + +/* + * MXU pool 19 + */ +enum { + OPC_MXU_Q8MUL =3D 0x00, + OPC_MXU_Q8MULSU =3D 0x01, +}; + +/* + * MXU pool 20 + */ +enum { + OPC_MXU_Q8MOVZ =3D 0x00, + OPC_MXU_Q8MOVN =3D 0x01, + OPC_MXU_D16MOVZ =3D 0x02, + OPC_MXU_D16MOVN =3D 0x03, + OPC_MXU_S32MOVZ =3D 0x04, + OPC_MXU_S32MOVN =3D 0x05, +}; + +/* + * MXU pool 21 + */ +enum { + OPC_MXU_Q8MAC =3D 0x00, + OPC_MXU_Q8MACSU =3D 0x01, +}; + =20 /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; --=20 2.7.4