From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153936258335510.001219113722755; Fri, 12 Oct 2018 09:43:03 -0700 (PDT) Received: from localhost ([::1]:41633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Wg-0008D3-2a for importer@patchew.org; Fri, 12 Oct 2018 12:42:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Ur-0007QT-Dl for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Uq-0002At-Kf for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45820 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Uq-000197-CF for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 547491A4132; Fri, 12 Oct 2018 18:40:02 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 37F841A246A; Fri, 12 Oct 2018 18:40:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:09 +0200 Message-Id: <1539362376-12010-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 01/28] elf: Fix PT_MIPS_XXX constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Fix existing and add missing PT_MIPS_XXX constants in elf.h. This is copied from kernel header arch/mips/include/asm/elf.h. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- include/elf.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/elf.h b/include/elf.h index 312f68a..decf210 100644 --- a/include/elf.h +++ b/include/elf.h @@ -28,8 +28,11 @@ typedef int64_t Elf64_Sxword; #define PT_PHDR 6 #define PT_LOPROC 0x70000000 #define PT_HIPROC 0x7fffffff -#define PT_MIPS_REGINFO 0x70000000 -#define PT_MIPS_OPTIONS 0x70000001 + +#define PT_MIPS_REGINFO 0x70000000 +#define PT_MIPS_RTPROC 0x70000001 +#define PT_MIPS_OPTIONS 0x70000002 +#define PT_MIPS_ABIFLAGS 0x70000003 =20 /* Flags in the e_flags field of the header */ /* MIPS architecture level. */ --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362776438403.19327520200557; Fri, 12 Oct 2018 09:46:16 -0700 (PDT) Received: from localhost ([::1]:41652 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Zr-0002UZ-4N for importer@patchew.org; Fri, 12 Oct 2018 12:46:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Va-0007s5-Vl for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0VV-0002ql-9o for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:50 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45958 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0VV-0001ne-1t for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:45 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2FBB11A4137; Fri, 12 Oct 2018 18:40:43 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 12F2B1A246A; Fri, 12 Oct 2018 18:40:43 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:10 +0200 Message-Id: <1539362376-12010-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 02/28] elf: Add MIPS_ABI_FP_XXX constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add MIPS_ABI_FP_XXX constants to elf.h. The source of information is kernel header arch/mips/include/asm/elf.h. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- include/elf.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/elf.h b/include/elf.h index decf210..eb5958d 100644 --- a/include/elf.h +++ b/include/elf.h @@ -87,6 +87,14 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson = 3A */ #define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection ma= sk */ =20 +#define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter = */ +#define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float = */ +#define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float = */ +#define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float = */ +#define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 = */ +#define MIPS_ABI_FP_XX 0x5 /* -mfpxx = */ +#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 = */ +#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spr= eg */ =20 /* These constants define the different elf file types */ #define ET_NONE 0 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362757171698.4314322667146; Fri, 12 Oct 2018 09:45:57 -0700 (PDT) Received: from localhost ([::1]:41649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0ZY-0002I3-3P for importer@patchew.org; Fri, 12 Oct 2018 12:45:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Uy-0007SX-5S for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Ut-0002Dt-6b for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:12 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46115 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Us-0002Cp-Uz for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:07 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B90EA1A4130; Fri, 12 Oct 2018 18:41:05 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9D6B11A246A; Fri, 12 Oct 2018 18:41:05 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:11 +0200 Message-Id: <1539362376-12010-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 03/28] elf: Add Mips_elf_abiflags_v0 structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add Mips_elf_abiflags_v0 structure to elf.h. The source of information is kernel header arch/mips/include/asm/elf.h. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- include/elf.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/elf.h b/include/elf.h index eb5958d..75c60cc 100644 --- a/include/elf.h +++ b/include/elf.h @@ -96,6 +96,21 @@ typedef int64_t Elf64_Sxword; #define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 = */ #define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spr= eg */ =20 +typedef struct mips_elf_abiflags_v0 { + uint16_t version; /* Version of flags structure = */ + uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 = */ + uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and bel= ow,*/ + /* 1-n otherwise = */ + uint8_t gpr_size; /* The size of general purpose registers = */ + uint8_t cpr1_size; /* The size of co-processor 1 registers = */ + uint8_t cpr2_size; /* The size of co-processor 2 registers = */ + uint8_t fp_abi; /* The floating-point ABI = */ + uint32_t isa_ext; /* Mask of processor-specific extensions = */ + uint32_t ases; /* Mask of ASEs used = */ + uint32_t flags1; /* Mask of general flags = */ + uint32_t flags2; +} Mips_elf_abiflags_v0; + /* These constants define the different elf file types */ #define ET_NONE 0 #define ET_REL 1 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362618405977.4762365131783; Fri, 12 Oct 2018 09:43:38 -0700 (PDT) Received: from localhost ([::1]:41634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XJ-0000RX-46 for importer@patchew.org; Fri, 12 Oct 2018 12:43:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0VM-0007h2-3F for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0VH-0002d1-4Y for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46163 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0VG-0002bO-Su for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:31 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 62EAE1A4132; Fri, 12 Oct 2018 18:41:29 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 474FD1A246A; Fri, 12 Oct 2018 18:41:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:12 +0200 Message-Id: <1539362376-12010-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 04/28] linux-user: Add MIPS-specific prctl() options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE and TARGET_PR_SET_FP_MODE. These values are essentially copied from linux kernel header include/uapi/linux/prctl.h. This is done in a way consistent with a similar case of aarch64-specific prctl() options TARGET_PR_SVE_SET_VL and TARGET_PR_SVE_GET_VL. Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic --- linux-user/mips/target_syscall.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_sysc= all.h index 2fca1c6..718680d 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -239,6 +239,10 @@ struct target_pt_regs { =20 #define TARGET_FORCE_SHMLBA =20 +/* MIPS-specific prctl() options */ +#define TARGET_PR_SET_FP_MODE 45 +#define TARGET_PR_GET_FP_MODE 46 + static inline abi_ulong target_shmlba(CPUMIPSState *env) { return 0x40000; --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362974663116.59299620008017; Fri, 12 Oct 2018 09:49:34 -0700 (PDT) Received: from localhost ([::1]:41664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0d3-0004y8-JY for importer@patchew.org; Fri, 12 Oct 2018 12:49:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Vd-0007uQ-LV for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Vd-0002yK-01 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46248 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Vc-0002wg-Ob for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:41:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id EC5401A4130; Fri, 12 Oct 2018 18:41:50 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id CF5731A246A; Fri, 12 Oct 2018 18:41:50 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:13 +0200 Message-Id: <1539362376-12010-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 05/28] linux-user: Add infrastructure for handling MIPS-specific prctl() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add infrastructure for handling MIPS-specific prctl(). This is, for now, just an empty placeholder. The real handling will be implemented in subsequent patches. Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic --- linux-user/syscall.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ae3c0df..d2cc971 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9347,6 +9347,14 @@ static abi_long do_syscall1(void *cpu_env, int num, = abi_long arg1, return ret; } #endif +#ifdef TARGET_MIPS + case TARGET_PR_GET_FP_MODE: + /* TODO: Implement TARGET_PR_SET_FP_MODE handling.*/ + return -TARGET_EINVAL; + case TARGET_PR_SET_FP_MODE: + /* TODO: Implement TARGET_PR_GET_FP_MODE handling.*/ + return -TARGET_EINVAL; +#endif /* MIPS */ #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: /* --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362665678888.7928599567235; Fri, 12 Oct 2018 09:44:25 -0700 (PDT) Received: from localhost ([::1]:41637 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Y4-00014m-H2 for importer@patchew.org; Fri, 12 Oct 2018 12:44:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0W1-0008AX-DE for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Vw-0003Gx-F6 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:17 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46390 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Vw-0003FX-71 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 16C7D1A4132; Fri, 12 Oct 2018 18:42:11 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id EF20C1A246A; Fri, 12 Oct 2018 18:42:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:14 +0200 Message-Id: <1539362376-12010-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 06/28] linux-user: Add fields that correspond to kernel arch_elf_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add fields that correspond to kernel arch_elf_state. This is essentially copied from kernel arch/mips/kernel/elf.c. Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- linux-user/qemu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index b4959e4..e5e7bcd 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -60,6 +60,15 @@ struct image_info { abi_ulong pt_dynamic_addr; abi_ulong interpreter_loadmap_addr; abi_ulong interpreter_pt_dynamic_addr; + + /* The fields that correspond to kernel arch_elf_state structure. = */ +#if defined TARGET_MIPS + uint32_t nan_2008; + uint32_t fp_abi; + uint32_t interp_fp_abi; + uint32_t overall_fp_mode; +#endif /* TARGET_MIPS */ + struct image_info *other_info; }; =20 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362863106887.92330822968; Fri, 12 Oct 2018 09:47:43 -0700 (PDT) Received: from localhost ([::1]:41656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0bF-0003VI-Vc for importer@patchew.org; Fri, 12 Oct 2018 12:47:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0WK-0008Vk-P4 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0WD-0003XV-Q1 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:34 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46438 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0WD-0003Vx-0X for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:29 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C025F1A4130; Fri, 12 Oct 2018 18:42:27 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A4E491A246A; Fri, 12 Oct 2018 18:42:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:15 +0200 Message-Id: <1539362376-12010-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 07/28] linux-user: Add the field for kernel thread info flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add the field for kernel thread info flags. This is essentially copied form kernel header mips/include/asm/thread_info.h. Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- linux-user/qemu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index e5e7bcd..57f3004 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -23,6 +23,13 @@ */ #define SIGSET_T_SIZE (_NSIG / 8) =20 +#if defined TARGET_MIPS +#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */ +#define TIF_HYBRID_FPREGS 28 /* 64b FP registers, odd singles */ + /* in bits 63:32 of even doubles */ +#define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */ +#endif /* TARGET_MIPS */ + /* This struct is used to hold certain information about the image. * Basically, it replicates in user space what would be certain * task_struct fields in the kernel @@ -69,6 +76,11 @@ struct image_info { uint32_t overall_fp_mode; #endif /* TARGET_MIPS */ =20 + /* The fields that correspond to kernel thread info flags. */ +#if defined TARGET_MIPS + abi_ulong thread_info_flags; +#endif /* TARGET_MIPS */ + struct image_info *other_info; }; =20 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362960326508.5362786081773; Fri, 12 Oct 2018 09:49:20 -0700 (PDT) Received: from localhost ([::1]:41661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0cm-0004kS-4H for importer@patchew.org; Fri, 12 Oct 2018 12:49:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0WZ-0000MH-Ae for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0WT-0003ov-MY for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:50 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46484 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0WR-0003md-OD for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:45 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 43FF21A4131; Fri, 12 Oct 2018 18:42:42 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 25E5E1A246A; Fri, 12 Oct 2018 18:42:42 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:16 +0200 Message-Id: <1539362376-12010-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 08/28] target/mips: Add CPO PWBase register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add PWBase register (CP0 Register 5, Select 5). The PWBase register contains the Page Table Base virtual address. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/machine.c | 5 +++-- target/mips/translate.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 28af4d1..c8999a8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -289,6 +289,7 @@ struct CPUMIPSState { #define CP0SC2_XR 56 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_M= ASK) + target_ulong CP0_PWBase; int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; diff --git a/target/mips/machine.c b/target/mips/machine.c index 5ba78ac..3592bb7 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 11, - .minimum_version_id =3D 11, + .version_id =3D 12, + .minimum_version_id =3D 12, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -256,6 +256,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), + VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb..7af9a21 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1929,6 +1929,17 @@ static inline void check_xnp(DisasContext *ctx) =20 /* * This code generates a "reserved instruction" exception if the + * Config3 PW bit is NOT set. + */ +static inline void check_pw(DisasContext *ctx) +{ + if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { + generate_exception_end(ctx, EXCP_RI); + } +} + +/* + * This code generates a "reserved instruction" exception if the * Config3 MT bit is NOT set. */ static inline void check_mt(DisasContext *ctx) @@ -5537,6 +5548,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) tcg_gen_ext32s_tl(arg, arg); rn =3D "SegCtl2"; break; + case 5: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); + rn =3D "PWBase"; + break; default: goto cp0_unimplemented; } @@ -6238,6 +6254,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_segctl2(cpu_env, arg); rn =3D "SegCtl2"; break; + case 5: + check_pw(ctx); + gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); + rn =3D "PWBase"; + break; default: goto cp0_unimplemented; } @@ -6948,6 +6969,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); rn =3D "SegCtl2"; break; + case 5: + check_pw(ctx); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); + rn =3D "PWBase"; + break; default: goto cp0_unimplemented; } @@ -7631,6 +7657,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_segctl2(cpu_env, arg); rn =3D "SegCtl2"; break; + case 5: + check_pw(ctx); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); + rn =3D "PWBase"; + break; default: goto cp0_unimplemented; } --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539362811877194.84821332279523; Fri, 12 Oct 2018 09:46:51 -0700 (PDT) Received: from localhost ([::1]:41653 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0aQ-0002vX-IY for importer@patchew.org; Fri, 12 Oct 2018 12:46:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Wi-0000RN-M2 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0We-00040y-2q for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46569 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Wd-0003zZ-NI for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:42:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9F4231A4131; Fri, 12 Oct 2018 18:42:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7FCCD1A246A; Fri, 12 Oct 2018 18:42:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:17 +0200 Message-Id: <1539362376-12010-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 09/28] target/mips: Add CPO PWField register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 6 ++++++ target/mips/helper.h | 1 + target/mips/machine.c | 5 +++-- target/mips/op_helper.c | 34 ++++++++++++++++++++++++++++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 5 files changed, 64 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c8999a8..01cd65c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -290,6 +290,12 @@ struct CPUMIPSState { #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_M= ASK) target_ulong CP0_PWBase; + target_ulong CP0_PWField; +#define CP0PF_GDI 24 /* 29..24 */ +#define CP0PF_UDI 18 /* 23..18 */ +#define CP0PF_MDI 12 /* 17..12 */ +#define CP0PF_PTI 6 /* 11..6 */ +#define CP0PF_PTEI 0 /* 5..0 */ int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; diff --git a/target/mips/helper.h b/target/mips/helper.h index b2a780a..6366f9b 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -120,6 +120,7 @@ DEF_HELPER_2(mtc0_pagegrain, void, env, tl) DEF_HELPER_2(mtc0_segctl0, void, env, tl) DEF_HELPER_2(mtc0_segctl1, void, env, tl) DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) DEF_HELPER_2(mtc0_wired, void, env, tl) DEF_HELPER_2(mtc0_srsconf0, void, env, tl) DEF_HELPER_2(mtc0_srsconf1, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 3592bb7..7aa496c 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 12, - .minimum_version_id =3D 12, + .version_id =3D 13, + .minimum_version_id =3D 13, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -257,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), + VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c148b31..bc506de 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1445,6 +1445,40 @@ void helper_mtc0_segctl2(CPUMIPSState *env, target_u= long arg1) tlb_flush(cs); } =20 +void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) +{ +#ifdef TARGET_MIPS64 + env->CP0_PWField =3D arg1 & 0x3F3FFFFFFFULL; +#else + uint32_t mask =3D 0x3FFFFFFF; + uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3F; + uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3F; + + if ((env->insn_flags & ISA_MIPS32R6)) { + if (((arg1 >> CP0PF_GDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_GDI); + } + if (((arg1 >> CP0PF_UDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_UDI); + } + if (((arg1 >> CP0PF_MDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_MDI); + } + if (((arg1 >> CP0PF_PTI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_PTI); + } + } + env->CP0_PWField =3D arg1 & mask; + + if ((new_ptei >=3D 32) || + ((env->insn_flags & ISA_MIPS32R6) && + (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { + env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | + (old_ptei << CP0PF_PTEI); + } +#endif +} + void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 7af9a21..882a765 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5553,6 +5553,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -6259,6 +6264,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwfield(cpu_env, arg); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -6974,6 +6984,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -7662,6 +7677,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwfield(cpu_env, arg); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363053402240.69696850662467; Fri, 12 Oct 2018 09:50:53 -0700 (PDT) Received: from localhost ([::1]:41673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0eK-00067J-8a for importer@patchew.org; Fri, 12 Oct 2018 12:50:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0X4-0000l4-F4 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Ws-0004Lf-TY for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:18 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46626 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Wp-0004Ei-Jr for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:08 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BA7B91A4132; Fri, 12 Oct 2018 18:43:03 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9B02E1A246A; Fri, 12 Oct 2018 18:43:03 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:18 +0200 Message-Id: <1539362376-12010-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 10/28] target/mips: Add CPO PWSize register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 7 +++++++ target/mips/helper.h | 1 + target/mips/machine.c | 5 +++-- target/mips/op_helper.c | 9 +++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 5 files changed, 40 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 01cd65c..a6abd1f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -296,6 +296,13 @@ struct CPUMIPSState { #define CP0PF_MDI 12 /* 17..12 */ #define CP0PF_PTI 6 /* 11..6 */ #define CP0PF_PTEI 0 /* 5..0 */ + target_ulong CP0_PWSize; +#define CP0PS_PS 30 +#define CP0PS_GDW 24 /* 29..24 */ +#define CP0PS_UDW 18 /* 23..18 */ +#define CP0PS_MDW 12 /* 17..12 */ +#define CP0PS_PTW 6 /* 11..6 */ +#define CP0PS_PTEW 0 /* 5..0 */ int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; diff --git a/target/mips/helper.h b/target/mips/helper.h index 6366f9b..169890a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl) DEF_HELPER_2(mtc0_segctl1, void, env, tl) DEF_HELPER_2(mtc0_segctl2, void, env, tl) DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) DEF_HELPER_2(mtc0_wired, void, env, tl) DEF_HELPER_2(mtc0_srsconf0, void, env, tl) DEF_HELPER_2(mtc0_srsconf1, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 7aa496c..3da891f 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 13, - .minimum_version_id =3D 13, + .version_id =3D 14, + .minimum_version_id =3D 14, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -258,6 +258,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), + VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index bc506de..0986baf 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1479,6 +1479,15 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_u= long arg1) #endif } =20 +void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) +{ +#ifdef TARGET_MIPS64 + env->CP0_PWSize =3D arg1 & 0x3F7FFFFFFFULL; +#else + env->CP0_PWSize =3D arg1 & 0x3FFFFFFF; +#endif +} + void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 882a765..ef38be9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5558,6 +5558,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); rn =3D "PWField"; break; + case 7: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); + rn =3D "PWSize"; + break; default: goto cp0_unimplemented; } @@ -6269,6 +6274,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_pwfield(cpu_env, arg); rn =3D "PWField"; break; + case 7: + check_pw(ctx); + gen_helper_mtc0_pwsize(cpu_env, arg); + rn =3D "PWSize"; + break; default: goto cp0_unimplemented; } @@ -6989,6 +6999,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); rn =3D "PWField"; break; + case 7: + check_pw(ctx); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)= ); + rn =3D "PWSize"; + break; default: goto cp0_unimplemented; } @@ -7682,6 +7697,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_pwfield(cpu_env, arg); rn =3D "PWField"; break; + case 7: + check_pw(ctx); + gen_helper_mtc0_pwsize(cpu_env, arg); + rn =3D "PWSize"; + break; default: goto cp0_unimplemented; } --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363013499187.1226670125618; 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Fri, 12 Oct 2018 18:43:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:19 +0200 Message-Id: <1539362376-12010-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 11/28] target/mips: Add CPO PWCtl register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 5 +++++ target/mips/helper.h | 1 + target/mips/machine.c | 5 +++-- target/mips/op_helper.c | 10 ++++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 5 files changed, 39 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a6abd1f..5e45e97 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -304,6 +304,11 @@ struct CPUMIPSState { #define CP0PS_PTW 6 /* 11..6 */ #define CP0PS_PTEW 0 /* 5..0 */ int32_t CP0_Wired; + int32_t CP0_PWCtl; +#define CP0PC_PWEN 31 +#define CP0PC_DPH 7 +#define CP0PC_HUGEPG 6 +#define CP0PC_PSN 0 /* 5..0 */ int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; #define CP0SRSC0_M 31 diff --git a/target/mips/helper.h b/target/mips/helper.h index 169890a..c23e4e5 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -129,6 +129,7 @@ DEF_HELPER_2(mtc0_srsconf2, void, env, tl) DEF_HELPER_2(mtc0_srsconf3, void, env, tl) DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 3da891f..70a8909 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 14, - .minimum_version_id =3D 14, + .version_id =3D 15, + .minimum_version_id =3D 15, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -260,6 +260,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), + VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0986baf..e649bd0 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1524,6 +1524,16 @@ void helper_mtc0_srsconf4(CPUMIPSState *env, target_= ulong arg1) env->CP0_SRSConf4 |=3D arg1 & env->CP0_SRSConf4_rw_bitmask; } =20 +void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1) +{ +#ifdef TARGET_MIPS64 + /* PWEn =3D 0. Hardware page table walking is not implemented. */ + env->CP0_PWCtl =3D (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); +#else + env->CP0_PWCtl =3D (arg1 & 0x800000FF); +#endif +} + void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) { uint32_t mask =3D 0x0000000F; diff --git a/target/mips/translate.c b/target/mips/translate.c index ef38be9..f669d48 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5598,6 +5598,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); rn =3D "SRSConf4"; break; + case 6: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); + rn =3D "PWCtl"; + break; default: goto cp0_unimplemented; } @@ -6314,6 +6319,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_srsconf4(cpu_env, arg); rn =3D "SRSConf4"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwctl(cpu_env, arg); + rn =3D "PWCtl"; + break; default: goto cp0_unimplemented; } @@ -7039,6 +7049,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); rn =3D "SRSConf4"; break; + case 6: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); + rn =3D "PWCtl"; + break; default: goto cp0_unimplemented; } @@ -7737,6 +7752,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_srsconf4(cpu_env, arg); rn =3D "SRSConf4"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwctl(cpu_env, arg); + rn =3D "PWCtl"; + break; default: goto cp0_unimplemented; } --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363189085432.28321808576015; Fri, 12 Oct 2018 09:53:09 -0700 (PDT) Received: from localhost ([::1]:41682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0gW-0007oI-1j for importer@patchew.org; Fri, 12 Oct 2018 12:53:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XM-0000yW-OF for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XH-0004oD-0e for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:39 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46727 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XG-0004iv-NN for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2C2571A413B; Fri, 12 Oct 2018 18:43:30 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0E3541A4138; Fri, 12 Oct 2018 18:43:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:20 +0200 Message-Id: <1539362376-12010-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 12/28] target/mips: Add reset state for PWSize and PWField registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add reset state for PWSize and PWField registers. The reset state is different for pre-R6 and R6 (and post-R6) ISAa. Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index f669d48..5e508d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25890,6 +25890,24 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |=3D (1 << CP0St_FR); } =20 + if (env->insn_flags & ISA_MIPS32R6) { + /* PTW =3D 1 */ + env->CP0_PWSize =3D 0x40; + /* GDI =3D 12 */ + /* UDI =3D 12 */ + /* MDI =3D 12 */ + /* PRI =3D 12 */ + /* PTEI =3D 2 */ + env->CP0_PWField =3D 0x0C30C302; + } else { + /* GDI =3D 0 */ + /* UDI =3D 0 */ + /* MDI =3D 0 */ + /* PRI =3D 0 */ + /* PTEI =3D 2 */ + env->CP0_PWField =3D 0x02; + } + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { /* microMIPS on reset when Config3.ISA is 3 */ env->hflags |=3D MIPS_HFLAG_M16; --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153936315647256.45642780446133; Fri, 12 Oct 2018 09:52:36 -0700 (PDT) Received: from localhost ([::1]:41681 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0fz-0007OD-6g for importer@patchew.org; Fri, 12 Oct 2018 12:52:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XR-00012w-3R for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XP-00051g-G6 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:45 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46751 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XP-00050D-3E for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:43 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 03A901A4130; Fri, 12 Oct 2018 18:43:42 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D77101A246A; Fri, 12 Oct 2018 18:43:41 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:21 +0200 Message-Id: <1539362376-12010-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 13/28] target/mips: Implement hardware page table walker X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Implement hardware page table walker. Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/helper.c | 369 ++++++++++++++++++++++++++++++++++++++++++++= +++- target/mips/internal.h | 1 + target/mips/op_helper.c | 7 +- 3 files changed, 374 insertions(+), 3 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index f0c268b..2b166cc 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -537,6 +537,346 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) } #endif =20 +#if !defined(CONFIG_USER_ONLY) +#if !defined(TARGET_MIPS64) + +/* Perform hardware page table walk +* +* Memory accesses are performed using the KERNEL privilege level. +* Synchronous exceptions detected on memory accesses cause a silent exit +* from page table walking, resulting in a TLB or XTLB Refill exception. +* +* Implementations are not required to support page table walk memory +* accesses from mapped memory regions. When an unsupported access is +* attempted, a silent exit is taken, resulting in a TLB or XTLB Refill +* exception. +* +* Note that if an exception is caused by AddressTranslation or LoadMemory +* functions, the exception is not taken, a silent exit is taken, +* resulting in a TLB or XTLB Refill exception. +*/ + +static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, + uint64_t *pte) +{ + if ((vaddr & ((entry_size >> 3) - 1)) !=3D 0) { + return false; + } + if (entry_size =3D=3D 64) { + *pte =3D cpu_ldq_code(env, vaddr); + } else { + *pte =3D cpu_ldl_code(env, vaddr); + } + return true; +} + +static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, + int entry_size, int ptei) +{ + uint64_t result =3D entry; + uint64_t rixi; + if (ptei > entry_size) { + ptei -=3D 32; + } + result >>=3D (ptei - 2); + rixi =3D result & 3; + result >>=3D 2; + result |=3D rixi << CP0EnLo_XI; + return result; +} + +static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, + int directory_index, bool *huge_page, bool *hgpg_directory_hit, + uint64_t *pw_entrylo0, uint64_t *pw_entrylo1) +{ + int dph =3D (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; + int psn =3D (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; + int hugepg =3D (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; + int ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3F; + int ptew =3D (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; + int native_shift =3D (((env->CP0_PWSize >> CP0PS_PS) & 1) =3D=3D 0) ? = 2 : 3; + int directory_shift =3D (ptew > 1) ? -1 : + (hugepg && (ptew =3D=3D 1)) ? native_shift + 1 : native_shift; + int leaf_shift =3D (ptew > 1) ? -1 : + (ptew =3D=3D 1) ? native_shift + 1 : native_shift; + uint32_t direntry_size =3D 1 << (directory_shift + 3); + uint32_t leafentry_size =3D 1 << (leaf_shift + 3); + + uint64_t entry; + uint64_t paddr; + int prot; + uint64_t lsb =3D 0; + uint64_t w =3D 0; + + if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, + ACCESS_INT, cpu_mmu_index(env, false)) + !=3D TLBRET_MATCH) { + /* wrong base address */ + return 0; + } + if (!get_pte(env, *vaddr, direntry_size, &entry)) { + return 0; + } + + if ((entry & (1 << psn)) && hugepg) { + *huge_page =3D true; + *hgpg_directory_hit =3D true; + entry =3D get_tlb_entry_layout(env, entry, leafentry_size, + ptei); + w =3D directory_index - 1; + if (directory_index & 0x1) { + /* generate adjacent page from same PTE for odd TLB page */ + lsb =3D (1 << w) >> 6; + *pw_entrylo0 =3D entry & ~lsb; /* even page */ + *pw_entrylo1 =3D entry | lsb; /* odd page */ + } else if (dph) { + int oddpagebit =3D 1 << leaf_shift; + uint64_t vaddr2 =3D *vaddr ^ oddpagebit; + if (*vaddr & oddpagebit) { + *pw_entrylo1 =3D entry; + } else { + *pw_entrylo0 =3D entry; + } + if (get_physical_address(env, &paddr, &prot, vaddr2, + MMU_DATA_LOAD, ACCESS_INT, + cpu_mmu_index(env, false)) + !=3D TLBRET_MATCH) { + return 0; + } + if (!get_pte(env, vaddr2, leafentry_size, &entry)) { + return 0; + } + entry =3D get_tlb_entry_layout(env, entry, + leafentry_size, ptei); + if (*vaddr & oddpagebit) { + *pw_entrylo0 =3D entry; + } else { + *pw_entrylo1 =3D entry; + } + } else { + return 0; + } + return 1; + } else { + *vaddr =3D entry; + return 2; + } +} + +static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int r= w, + int mmu_idx) +{ + int gdw =3D (env->CP0_PWSize >> CP0PS_GDW) & 0x3f; + int udw =3D (env->CP0_PWSize >> CP0PS_UDW) & 0x3f; + int mdw =3D (env->CP0_PWSize >> CP0PS_MDW) & 0x3f; + int ptw =3D (env->CP0_PWSize >> CP0PS_PTW) & 0x3F; + + /* Initial values */ + bool huge_page =3D false; + bool hgpg_bdhit =3D false; + bool hgpg_gdhit =3D false; + bool hgpg_udhit =3D false; + bool hgpg_mdhit =3D false; + + int32_t pw_pagemask =3D 0; + target_ulong pw_entryhi =3D 0; + uint64_t pw_entrylo0 =3D 0; + uint64_t pw_entrylo1 =3D 0; + + /* Native pointer size */ + /*For the 32-bit architectures, this bit is fixed to 0.*/ + int native_shift =3D (((env->CP0_PWSize >> CP0PS_PS) & 1) =3D=3D 0) ? = 2 : 3; + + /* Indices from PWField */ + int gdi =3D (env->CP0_PWField >> CP0PF_GDI) & 0x3F; + int udi =3D (env->CP0_PWField >> CP0PF_UDI) & 0x3F; + int mdi =3D (env->CP0_PWField >> CP0PF_MDI) & 0x3F; + int pti =3D (env->CP0_PWField >> CP0PF_PTI) & 0x3F; + int ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3F; + int ptew =3D (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; + + /* Indices computed from faulting address */ + int gindex =3D (address >> gdi) & ((1 << gdw) - 1); + int uindex =3D (address >> udi) & ((1 << udw) - 1); + int mindex =3D (address >> mdi) & ((1 << mdw) - 1); + int ptindex =3D (address >> pti) & ((1 << ptw) - 1); + + /* Other HTW configs */ + int hugepg =3D (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; + + /* HTW Shift values (depend on entry size) */ + int directory_shift =3D (ptew > 1) ? -1 : + (hugepg && (ptew =3D=3D 1)) ? native_shift + 1 : native_shift; + int leaf_shift =3D (ptew > 1) ? -1 : + (ptew =3D=3D 1) ? native_shift + 1 : native_shift; + + /* Offsets into tables */ + int goffset =3D gindex << directory_shift; + int uoffset =3D uindex << directory_shift; + int moffset =3D mindex << directory_shift; + int ptoffset0 =3D (ptindex >> 1) << (leaf_shift + 1); + int ptoffset1 =3D ptoffset0 | (1 << (leaf_shift)); + + uint32_t leafentry_size =3D 1 << (leaf_shift + 3); + + /* Starting address - Page Table Base */ + uint64_t vaddr =3D env->CP0_PWBase; + + uint64_t dir_entry; + uint64_t paddr; + int prot; + int m; + + if (!(env->CP0_Config3 & (1 << CP0C3_PW))) { + /* walker is unimplemented */ + return false; + } + if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) { + /* walker is disabled */ + return false; + } + if (!(gdw > 0 || udw > 0 || mdw > 0)) { + /* no structure to walk */ + return false; + } + if ((directory_shift =3D=3D -1) || (leaf_shift =3D=3D -1)) { + return false; + } + + /* Global Directory */ + if (gdw > 0) { + vaddr |=3D goffset; + switch (walk_directory(env, &vaddr, + gdi, &huge_page, &hgpg_gdhit, + &pw_entrylo0, &pw_entrylo1)) { + case 0: + return false; + case 1: + goto refill; + case 2: + default: + break; + } + } + + /* Upper directory */ + if (udw > 0) { + vaddr |=3D uoffset; + switch (walk_directory(env, &vaddr, + udi, &huge_page, &hgpg_udhit, + &pw_entrylo0, &pw_entrylo1)) { + case 0: + return false; + case 1: + goto refill; + case 2: + default: + break; + } + } + + /* Middle directory */ + if (mdw > 0) { + vaddr |=3D moffset; + switch (walk_directory(env, &vaddr, + mdi, &huge_page, &hgpg_mdhit, + &pw_entrylo0, &pw_entrylo1)) { + case 0: + return false; + case 1: + goto refill; + case 2: + default: + break; + } + } + + /* Leaf Level Page Table - First half of PTE pair */ + vaddr |=3D ptoffset0; + if (get_physical_address(env, &paddr, &prot, vaddr, + MMU_DATA_LOAD, ACCESS_INT, + cpu_mmu_index(env, false)) + !=3D TLBRET_MATCH) { + return false; + } + if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + return false; + } + dir_entry =3D get_tlb_entry_layout(env, dir_entry, leafentry_size, pte= i); + pw_entrylo0 =3D dir_entry; + + /* Leaf Level Page Table - Second half of PTE pair */ + vaddr |=3D ptoffset1; + if (get_physical_address(env, &paddr, &prot, vaddr, + MMU_DATA_LOAD, ACCESS_INT, + cpu_mmu_index(env, false)) !=3D TLBRET_MATCH)= { + return false; + } + if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + return false; + } + dir_entry =3D get_tlb_entry_layout(env, dir_entry, leafentry_size, pte= i); + pw_entrylo1 =3D dir_entry; + +refill: + m =3D (1 << pti) - 1; + + if (huge_page) { + switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 | + hgpg_mdhit) { + case 4: + m =3D (1 << gdi) - 1; + if (gdi & 1) { + m >>=3D 1; + } + break; + case 2: + m =3D (1 << udi) - 1; + if (udi & 1) { + m >>=3D 1; + } + break; + case 1: + m =3D (1 << mdi) - 1; + if (mdi & 1) { + m >>=3D 1; + } + break; + } + } + + pw_pagemask =3D m >> 12; + update_pagemask(env, pw_pagemask << 13, &pw_pagemask); + pw_entryhi =3D (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); + + { + target_ulong tmp_entryhi =3D env->CP0_EntryHi; + int32_t tmp_pagemask =3D env->CP0_PageMask; + uint64_t tmp_entrylo0 =3D env->CP0_EntryLo0; + uint64_t tmp_entrylo1 =3D env->CP0_EntryLo1; + + env->CP0_EntryHi =3D pw_entryhi; + env->CP0_PageMask =3D pw_pagemask; + env->CP0_EntryLo0 =3D pw_entrylo0; + env->CP0_EntryLo1 =3D pw_entrylo1; + + /* + * The hardware page walker inserts a page into the TLB in a manner + * identical to a TLBWR instruction as executed by the software re= fill + * handler. + */ + r4k_helper_tlbwr(env); + + env->CP0_EntryHi =3D tmp_entryhi; + env->CP0_PageMask =3D tmp_pagemask; + env->CP0_EntryLo0 =3D tmp_entrylo0; + env->CP0_EntryLo1 =3D tmp_entrylo1; + } + return true; +} +#endif +#endif + int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, int mmu_idx) { @@ -558,8 +898,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addre= ss, int size, int rw, =20 /* data access */ #if !defined(CONFIG_USER_ONLY) - /* XXX: put correct access by using cpu_restore_state() - correctly */ + /* XXX: put correct access by using cpu_restore_state() correctly */ access_type =3D ACCESS_INT; ret =3D get_physical_address(env, &physical, &prot, address, rw, access_type, mmu_idx); @@ -583,6 +922,32 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, } else if (ret < 0) #endif { +#if !defined(CONFIG_USER_ONLY) +#if !defined(TARGET_MIPS64) + if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { + /* + * Memory reads during hardware page table walking are perform= ed + * as if they were kernel-mode load instructions. + */ + int mode =3D (env->hflags & MIPS_HFLAG_KSU); + bool ret_walker; + env->hflags &=3D ~MIPS_HFLAG_KSU; + ret_walker =3D page_table_walk_refill(env, address, rw, mmu_id= x); + env->hflags |=3D mode; + if (ret_walker) { + ret =3D get_physical_address(env, &physical, &prot, + address, rw, access_type, mmu_i= dx); + if (ret =3D=3D TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + ret =3D 0; + return ret; + } + } + } +#endif +#endif raise_mmu_exception(env, address, rw, ret); ret =3D 1; } diff --git a/target/mips/internal.h b/target/mips/internal.h index e41051f..2898bfc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -211,6 +211,7 @@ uint64_t float_class_d(uint64_t arg, float_status *fst); =20 extern unsigned int ieee_rm[]; int ieee_ex_to_mips(int xcpt); +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 static inline void restore_rounding_mode(CPUMIPSState *env) { diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e649bd0..af130f6 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1400,7 +1400,7 @@ void helper_mtc0_context(CPUMIPSState *env, target_ul= ong arg1) env->CP0_Context =3D (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007F= FFFF); } =20 -void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk) { uint64_t mask =3D arg1 >> (TARGET_PAGE_BITS + 1); if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 =3D=3D ~0) || @@ -1411,6 +1411,11 @@ void helper_mtc0_pagemask(CPUMIPSState *env, target_= ulong arg1) } } =20 +void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) +{ + update_pagemask(env, arg1, &env->CP0_PageMask); +} + void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) { /* SmartMIPS not implemented */ --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153936350918554.90849965327618; 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Fri, 12 Oct 2018 18:43:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:22 +0200 Message-Id: <1539362376-12010-15-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 14/28] target/mips: Extend WatchHi registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/DMFC0 in 64-bit architectures. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/helper.h | 3 +++ target/mips/machine.c | 2 +- target/mips/op_helper.c | 23 +++++++++++++++++++++-- target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 65 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5e45e97..10c3813 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -531,7 +531,7 @@ struct CPUMIPSState { uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; - int32_t CP0_WatchHi[8]; + uint64_t CP0_WatchHi[8]; #define CP0WH_ASID 16 target_ulong CP0_XContext; int32_t CP0_Framemask; diff --git a/target/mips/helper.h b/target/mips/helper.h index c23e4e5..0ec500a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -76,6 +76,7 @@ DEF_HELPER_1(mfc0_maar, tl, env) DEF_HELPER_1(mfhc0_maar, tl, env) DEF_HELPER_2(mfc0_watchlo, tl, env, i32) DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) DEF_HELPER_1(mfc0_debug, tl, env) DEF_HELPER_1(mftc0_debug, tl, env) #ifdef TARGET_MIPS64 @@ -87,6 +88,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -153,6 +155,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl) DEF_HELPER_2(mtc0_maari, void, env, tl) DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) DEF_HELPER_2(mtc0_xcontext, void, env, tl) DEF_HELPER_2(mtc0_framemask, void, env, tl) DEF_HELPER_2(mtc0_debug, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 70a8909..5d558c1 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -292,7 +292,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), VMSTATE_UINT64(env.lladdr, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), - VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), + VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), VMSTATE_INT32(env.CP0_Debug, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index af130f6..3d86c60 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -991,7 +991,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, ui= nt32_t sel) =20 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) { - return env->CP0_WatchHi[sel]; + return (int32_t) env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel] >> 32; } =20 target_ulong helper_mfc0_debug(CPUMIPSState *env) @@ -1059,6 +1064,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env,= uint32_t sel) { return env->CP0_WatchLo[sel]; } + +target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1818,11 +1828,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_= ulong arg1, uint32_t sel) =20 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) { - int mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + uint64_t mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_AS= ID); + if ((env->CP0_Config5 >> CP0C5_MI) & 1) { + mask |=3D 0xFFFFFFFF00000000ULL; /* MMID */ + } env->CP0_WatchHi[sel] =3D arg1 & mask; env->CP0_WatchHi[sel] &=3D ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } =20 +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t s= el) +{ + env->CP0_WatchHi[sel] =3D ((uint64_t) (arg1) << 32) | + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL= ); +} + void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) { target_ulong mask =3D (1ULL << (env->SEGBITS - 7)) - 1; diff --git a/target/mips/translate.c b/target/mips/translate.c index 5e508d5..c7eaee7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5223,6 +5223,25 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 19: + switch (sel) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* upper 32 bits are only available when Config5MI !=3D 0 */ + /* CP0_CHECK(ctx->mi); */ + gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel])= , 0); + rn =3D "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case 28: switch (sel) { case 0: @@ -5295,6 +5314,25 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 19: + switch (sel) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* upper 32 bits are only available when Config5MI !=3D 0 */ + /* CP0_CHECK(ctx->mi); */ + gen_helper_0e1i(mthc0_watchhi, arg, sel); + rn =3D "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case 28: switch (sel) { case 0: @@ -7293,7 +7331,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 6: case 7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); - gen_helper_1e0i(mfc0_watchhi, arg, sel); + gen_helper_1e0i(dmfc0_watchhi, arg, sel); rn =3D "WatchHi"; break; default: --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363366288499.3359118564373; Fri, 12 Oct 2018 09:56:06 -0700 (PDT) Received: from localhost ([::1]:41700 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0jN-0001xJ-8m for importer@patchew.org; Fri, 12 Oct 2018 12:56:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XZ-0001AT-Fd for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XV-00058f-AT for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46830 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XV-00057N-2I for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:49 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C3F6B1A4140; Fri, 12 Oct 2018 18:43:47 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A0A141A4131; Fri, 12 Oct 2018 18:43:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:23 +0200 Message-Id: <1539362376-12010-16-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 15/28] target/mips: Add CPO MemoryMapID register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add CPO MemoryMapID register. It is used by Global TLB Invalidate instruction (GINVT). Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/internal.h | 1 + target/mips/machine.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 10c3813..77c6355 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -252,6 +252,7 @@ struct CPUMIPSState { #define CP0GN_VPId 0 target_ulong CP0_Context; target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; + int32_t CP0_MemoryMapID; int32_t CP0_PageMask; int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; diff --git a/target/mips/internal.h b/target/mips/internal.h index 2898bfc..6888a06 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -91,6 +91,7 @@ struct r4k_tlb_t { target_ulong VPN; uint32_t PageMask; uint16_t ASID; + uint32_t MMID; unsigned int G:1; unsigned int C0:3; unsigned int C1:3; diff --git a/target/mips/machine.c b/target/mips/machine.c index 5d558c1..4c80724 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -136,6 +136,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size, = VMStateField *field) qemu_get_betls(f, &v->VPN); qemu_get_be32s(f, &v->PageMask); qemu_get_be16s(f, &v->ASID); + qemu_get_be32s(f, &v->MMID); qemu_get_be16s(f, &flags); v->G =3D (flags >> 10) & 1; v->C0 =3D (flags >> 7) & 3; @@ -161,6 +162,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size, = VMStateField *field, r4k_tlb_t *v =3D pv; =20 uint16_t asid =3D v->ASID; + uint32_t mmid =3D v->MMID; uint16_t flags =3D ((v->EHINV << 15) | (v->RI1 << 14) | (v->RI0 << 13) | @@ -177,6 +179,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size, = VMStateField *field, qemu_put_betls(f, &v->VPN); qemu_put_be32s(f, &v->PageMask); qemu_put_be16s(f, &asid); + qemu_put_be32s(f, &mmid); qemu_put_be16s(f, &flags); qemu_put_be64s(f, &v->PFN[0]); qemu_put_be64s(f, &v->PFN[1]); @@ -251,6 +254,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), + VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363239906482.991786882057; Fri, 12 Oct 2018 09:53:59 -0700 (PDT) Received: from localhost ([::1]:41685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0hF-000079-Jh for importer@patchew.org; Fri, 12 Oct 2018 12:53:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XZ-0001AS-Fb for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XV-00059S-MQ for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46837 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XV-00057b-6s for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:49 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E10011A246A; Fri, 12 Oct 2018 18:43:47 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id AFCB61A413C; Fri, 12 Oct 2018 18:43:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:24 +0200 Message-Id: <1539362376-12010-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim SAARI (Special Address Access Register Index) provides an index into the SAAR register to indicate whether the ITU or other block is being accessed. SAAR (Special Address Access Register) stores the base address where the ITU will be located, as well as the block size. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 7 +++++ target/mips/helper.h | 6 +++++ target/mips/internal.h | 1 + target/mips/machine.c | 2 ++ target/mips/op_helper.c | 51 +++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 68 +++++++++++++++++++++++++++++++++++++++++++++= +--- 6 files changed, 131 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 77c6355..dc0122d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -345,6 +345,12 @@ struct CPUMIPSState { uint32_t CP0_BadInstrP; uint32_t CP0_BadInstrX; int32_t CP0_Count; +#define CP0SAARI_IDX 0 + uint32_t CP0_SAARI; +#define CP0SAAR_BASE 12 +#define CP0SAAR_SIZE 1 +#define CP0SAAR_EN 0 + uint64_t CP0_SAAR[2]; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 target_ulong CP0_EntryHi_ASID_mask; @@ -635,6 +641,7 @@ struct CPUMIPSState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ int insn_flags; /* Supported instruction set */ + int saarp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/mips/helper.h b/target/mips/helper.h index 0ec500a..ba4a872 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -89,6 +91,7 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -133,6 +136,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/internal.h b/target/mips/internal.h index 6888a06..54bf39f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -61,6 +61,7 @@ struct mips_def_t { target_ulong CP0_EBaseWG_rw_bitmask; int insn_flags; enum mips_mmu_types mmu_type; + int32_t SAARP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/machine.c b/target/mips/machine.c index 4c80724..4761815 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -276,6 +276,8 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), + VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3d86c60..1fae357 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return count; } =20 +target_ulong helper_mfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + +target_ulong helper_mfhc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; + } + return 0; +} + target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -1069,6 +1085,15 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env,= uint32_t sel) { return env->CP0_WatchHi[sel]; } + +target_ulong helper_dmfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1580,6 +1605,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulo= ng arg1) qemu_mutex_unlock_iothread(); } =20 +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D arg1 & 0x3f; + if (target <=3D 1) { + env->CP0_SAARI =3D target; + } +} + +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + } +} + +void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D + (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | + (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + } +} + void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/translate.c b/target/mips/translate.c index c7eaee7..e9c3a14 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1473,6 +1473,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool saar; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -5207,6 +5208,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 9: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfhc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } + break; case 17: switch (sel) { case 0: @@ -5296,6 +5308,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 9: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mthc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } case 17: switch (sel) { case 0: @@ -5701,7 +5723,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -6406,7 +6437,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -7151,7 +7191,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_dmfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -7839,7 +7888,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -25437,6 +25495,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->saar =3D (bool) env->saarp; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; @@ -25802,6 +25861,7 @@ void cpu_state_reset(CPUMIPSState *env) env->active_fpu.fcr31 =3D env->cpu_model->CP1_fcr31; env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; + env->saarp =3D env->cpu_model->SAARP; =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363339007133.56341527193877; Fri, 12 Oct 2018 09:55:39 -0700 (PDT) Received: from localhost ([::1]:41694 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0iv-0001TU-Tk for importer@patchew.org; Fri, 12 Oct 2018 12:55:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54982) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XZ-0001AQ-FU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XV-00059K-LN for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46843 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XV-00057j-BV for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:49 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 22F3F1A4145; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id C0D151A4137; Fri, 12 Oct 2018 18:43:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:25 +0200 Message-Id: <1539362376-12010-18-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 17/28] target/mips: Add bit definitions for DSP R3 ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add DSP R3 ASE related bit definition for insn_flags and hflags. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/mips-defs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index dc0122d..f07b94e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -624,6 +624,7 @@ struct CPUMIPSState { /* MIPS DSP resources access. */ #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources.= */ #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resource= s. */ +#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resourc= es.*/ /* Extra flag about HWREna register. */ #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mod= e */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c8e9979..b27b7ae 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -47,6 +47,7 @@ #define ASE_MDMX 0x00040000 #define ASE_DSP 0x00080000 #define ASE_DSPR2 0x00100000 +#define ASE_DSPR3 0x02000000 #define ASE_MT 0x00200000 #define ASE_SMARTMIPS 0x00400000 #define ASE_MICROMIPS 0x00800000 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363141151839.8770635785698; Fri, 12 Oct 2018 09:52:21 -0700 (PDT) Received: from localhost ([::1]:41678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0fg-0007AA-9G for importer@patchew.org; Fri, 12 Oct 2018 12:52:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XZ-0001AU-Fj for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XW-00059x-2D for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46856 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XV-00057w-Lm for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:49 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 39C561A4142; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0D6BB1A4131; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:26 +0200 Message-Id: <1539362376-12010-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add infrastructure for availability control for DSP R3 ASE MIPS instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but this is likely to be changed in near future. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 11 ++++++++--- target/mips/translate.c | 13 ++++++++++++- target/mips/translate_init.inc.c | 3 ++- 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 54bf39f..e367d7e 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -310,8 +310,8 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | - MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | - MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); + MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | + MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); if (env->CP0_Status & (1 << CP0St_ERL)) { env->hflags |=3D MIPS_HFLAG_ERL; } @@ -358,7 +358,12 @@ static inline void compute_hflags(CPUMIPSState *env) (env->CP0_Config5 & (1 << CP0C5_SBRI))) { env->hflags |=3D MIPS_HFLAG_SBRI; } - if (env->insn_flags & ASE_DSPR2) { + if (env->insn_flags & ASE_DSPR3) { + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |=3D MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | + MIPS_HFLAG_DSPR3; + } + } else if (env->insn_flags & ASE_DSPR2) { /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, so enable to access DSPR2 resources. */ if (env->CP0_Status & (1 << CP0St_MX)) { diff --git a/target/mips/translate.c b/target/mips/translate.c index e9c3a14..c3ad65c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1869,6 +1869,17 @@ static inline void check_dspr2(DisasContext *ctx) } } =20 +static inline void check_dspr3(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) { + if (ctx->insn_flags & ASE_DSP) { + generate_exception_end(ctx, EXCP_DSPDIS); + } else { + generate_exception_end(ctx, EXCP_RI); + } + } +} + /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ static inline void check_insn(DisasContext *ctx, int flags) @@ -20285,7 +20296,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s); break; case NM_BPOSGE32C: - check_dspr2(ctx); + check_dspr3(ctx); { int32_t imm =3D extract32(ctx->opcode, 1, 13) | extract32(ctx->opcode, 0, 1) << 13; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index b3320b9..d7cd4ee 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT, + .insn_flags =3D CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | + ASE_MT, .mmu_type =3D MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539364040843699.8422665845546; Fri, 12 Oct 2018 10:07:20 -0700 (PDT) Received: from localhost ([::1]:41778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0uB-0002XJ-8X for importer@patchew.org; Fri, 12 Oct 2018 13:07:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KZ-UQ for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005O4-0h for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46889 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-000598-Cv for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6685B1A4155; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1C1261A4144; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:27 +0200 Message-Id: <1539362376-12010-20-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 19/28] target/mips: Improve DSP R2/R3-related naming X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Do following replacements: ASE_DSPR2 -> ASE_DSP_R2 ASE_DSPR3 -> ASE_DSP_R3 check_dspr2() -> check_dsp_r2() check_dspr3() -> check_dsp_r3() Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/internal.h | 4 +- target/mips/mips-defs.h | 4 +- target/mips/translate.c | 180 +++++++++++++++++++----------------= ---- target/mips/translate_init.inc.c | 8 +- 4 files changed, 98 insertions(+), 98 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index e367d7e..6cf00d8 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -358,12 +358,12 @@ static inline void compute_hflags(CPUMIPSState *env) (env->CP0_Config5 & (1 << CP0C5_SBRI))) { env->hflags |=3D MIPS_HFLAG_SBRI; } - if (env->insn_flags & ASE_DSPR3) { + if (env->insn_flags & ASE_DSP_R3) { if (env->CP0_Status & (1 << CP0St_MX)) { env->hflags |=3D MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | MIPS_HFLAG_DSPR3; } - } else if (env->insn_flags & ASE_DSPR2) { + } else if (env->insn_flags & ASE_DSP_R2) { /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, so enable to access DSPR2 resources. */ if (env->CP0_Status & (1 << CP0St_MX)) { diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b27b7ae..5b985b8 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -46,8 +46,8 @@ #define ASE_MIPS3D 0x00020000 #define ASE_MDMX 0x00040000 #define ASE_DSP 0x00080000 -#define ASE_DSPR2 0x00100000 -#define ASE_DSPR3 0x02000000 +#define ASE_DSP_R2 0x00100000 +#define ASE_DSP_R3 0x02000000 #define ASE_MT 0x00200000 #define ASE_SMARTMIPS 0x00400000 #define ASE_MICROMIPS 0x00800000 diff --git a/target/mips/translate.c b/target/mips/translate.c index c3ad65c..1d31051 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1858,7 +1858,7 @@ static inline void check_dsp(DisasContext *ctx) } } =20 -static inline void check_dspr2(DisasContext *ctx) +static inline void check_dsp_r2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { if (ctx->insn_flags & ASE_DSP) { @@ -1869,7 +1869,7 @@ static inline void check_dspr2(DisasContext *ctx) } } =20 -static inline void check_dspr3(DisasContext *ctx) +static inline void check_dsp_r3(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) { if (ctx->insn_flags & ASE_DSP) { @@ -17642,7 +17642,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, case NM_POOL32AXF_2_0_7: switch (extract32(ctx->opcode, 9, 3)) { case NM_DPA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpa_w_ph(t0, v1, v0, cpu_env); break; case NM_DPAQ_S_W_PH: @@ -17650,7 +17650,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env); break; case NM_DPS_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dps_w_ph(t0, v1, v0, cpu_env); break; case NM_DPSQ_S_W_PH: @@ -17665,7 +17665,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, case NM_POOL32AXF_2_8_15: switch (extract32(ctx->opcode, 9, 3)) { case NM_DPAX_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpax_w_ph(t0, v0, v1, cpu_env); break; case NM_DPAQ_SA_L_W: @@ -17673,7 +17673,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env); break; case NM_DPSX_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env); break; case NM_DPSQ_SA_L_W: @@ -17692,7 +17692,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env); break; case NM_DPAQX_S_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env); break; case NM_DPSU_H_QBL: @@ -17700,11 +17700,11 @@ static void gen_pool32axf_2_multiply(DisasContext= *ctx, uint32_t opc, gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env); break; case NM_DPSQX_S_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env); break; case NM_MULSA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); break; default: @@ -17719,7 +17719,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env); break; case NM_DPAQX_SA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env); break; case NM_DPSU_H_QBR: @@ -17727,7 +17727,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env); break; case NM_DPSQX_SA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env); break; case NM_MULSAQ_S_W_PH: @@ -17769,7 +17769,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd); break; case NM_BALIGN: - check_dspr2(ctx); + check_dsp_r2(ctx); if (rt !=3D 0) { gen_load_gpr(t0, rs); rd &=3D 3; @@ -17999,7 +17999,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, =20 switch (opc) { case NM_ABSQ_S_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_absq_s_qb(v0_t, v0_t, cpu_env); gen_store_gpr(v0_t, ret); break; @@ -18138,7 +18138,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, =20 switch (opc) { case NM_SHRA_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); tcg_gen_movi_tl(t0, rd >> 2); switch (extract32(ctx->opcode, 12, 1)) { case 0: @@ -18154,7 +18154,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; case NM_SHRL_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); tcg_gen_movi_tl(t0, rd >> 1); gen_helper_shrl_ph(t0, t0, rs_t); gen_store_gpr(t0, rt); @@ -19079,19 +19079,19 @@ static void gen_pool32a5_nanomips_insn(DisasConte= xt *ctx, int opc, gen_store_gpr(v1_t, ret); break; case NM_CMPGDU_EQ_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t); tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4); gen_store_gpr(v1_t, ret); break; case NM_CMPGDU_LT_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t); tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4); gen_store_gpr(v1_t, ret); break; case NM_CMPGDU_LE_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t); tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4); gen_store_gpr(v1_t, ret); @@ -19147,7 +19147,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_ADDQH_R_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDQH_PH */ @@ -19162,7 +19162,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_ADDQH_R_W: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDQH_W */ @@ -19192,7 +19192,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_ADDU_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDU_PH */ @@ -19207,7 +19207,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_ADDUH_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDUH_QB */ @@ -19237,7 +19237,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_SHRAV_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SHRAV_QB */ @@ -19267,7 +19267,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_SUBQH_R_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBQH_PH */ @@ -19282,7 +19282,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_SUBQH_R_W: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBQH_W */ @@ -19312,7 +19312,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_SUBU_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBU_PH */ @@ -19327,7 +19327,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_SUBUH_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBUH_QB */ @@ -19357,7 +19357,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_PRECR_SRA_R_PH_W: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* PRECR_SRA_PH_W */ @@ -19397,22 +19397,22 @@ static void gen_pool32a5_nanomips_insn(DisasConte= xt *ctx, int opc, gen_store_gpr(v1_t, ret); break; case NM_MULQ_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_RS_W: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_S_W: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env); gen_store_gpr(v1_t, ret); break; case NM_APPEND: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_load_gpr(t0, rs); if (rd !=3D 0) { tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd); @@ -19430,7 +19430,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, gen_store_gpr(v1_t, ret); break; case NM_SHRLV_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shrl_ph(v1_t, v1_t, v2_t); gen_store_gpr(v1_t, ret); break; @@ -19472,7 +19472,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, gen_store_gpr(v1_t, ret); break; case NM_MUL_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (extract32(ctx->opcode, 10, 1)) { case 0: /* MUL_PH */ @@ -19487,7 +19487,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; case NM_PRECR_QB_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_precr_qb_ph(v1_t, v1_t, v2_t); gen_store_gpr(v1_t, ret); break; @@ -20296,7 +20296,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s); break; case NM_BPOSGE32C: - check_dspr3(ctx); + check_dsp_r3(ctx); { int32_t imm =3D extract32(ctx->opcode, 1, 13) | extract32(ctx->opcode, 0, 1) << 13; @@ -20805,7 +20805,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, switch (op1) { /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ case OPC_MULT_G_2E: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (op2) { case OPC_ADDUH_QB: gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); @@ -20848,7 +20848,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, case OPC_ABSQ_S_PH_DSP: switch (op2) { case OPC_ABSQ_S_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env); break; case OPC_ABSQ_S_PH: @@ -20927,11 +20927,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDU_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDU_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBQ_PH: @@ -20955,11 +20955,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBU_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBU_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDSC: @@ -20983,7 +20983,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, case OPC_CMPU_EQ_QB_DSP: switch (op2) { case OPC_PRECR_QB_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); break; case OPC_PRECRQ_QB_PH: @@ -20991,7 +20991,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); break; case OPC_PRECR_SRA_PH_W: - check_dspr2(ctx); + check_dsp_r2(ctx); { TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, @@ -21000,7 +21000,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, break; } case OPC_PRECR_SRA_R_PH_W: - check_dspr2(ctx); + check_dsp_r2(ctx); { TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, @@ -21082,7 +21082,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); break; case OPC_ABSQ_S_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env); break; case OPC_ABSQ_S_PW: @@ -21126,19 +21126,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBU_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBU_S_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_SUBUH_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); break; case OPC_SUBUH_R_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); break; case OPC_ADDQ_PW: @@ -21166,19 +21166,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDU_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDU_S_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_ADDUH_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); break; case OPC_ADDUH_R_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); break; } @@ -21186,11 +21186,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, case OPC_CMPU_EQ_OB_DSP: switch (op2) { case OPC_PRECR_OB_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); break; case OPC_PRECR_SRA_QH_PW: - check_dspr2(ctx); + check_dsp_r2(ctx); { TCGv_i32 ret_t =3D tcg_const_i32(ret); gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); @@ -21198,7 +21198,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, break; } case OPC_PRECR_SRA_R_QH_PW: - check_dspr2(ctx); + check_dsp_r2(ctx); { TCGv_i32 sa_v =3D tcg_const_i32(ret); gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); @@ -21301,27 +21301,27 @@ static void gen_mipsdsp_shift(DisasContext *ctx, = uint32_t opc, gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); break; case OPC_SHRL_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); break; case OPC_SHRLV_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); break; case OPC_SHRA_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); break; case OPC_SHRA_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); break; case OPC_SHRAV_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); break; case OPC_SHRAV_R_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); break; case OPC_SHRA_PH: @@ -21400,19 +21400,19 @@ static void gen_mipsdsp_shift(DisasContext *ctx, = uint32_t opc, gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); break; case OPC_SHRA_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); break; case OPC_SHRAV_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); break; case OPC_SHRA_R_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); break; case OPC_SHRAV_R_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); break; case OPC_SHRA_PW: @@ -21456,11 +21456,11 @@ static void gen_mipsdsp_shift(DisasContext *ctx, = uint32_t opc, gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); break; case OPC_SHRL_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); break; case OPC_SHRLV_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); break; default: /* Invalid */ @@ -21501,7 +21501,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx,= uint32_t op1, uint32_t op2, /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ case OPC_MULT_G_2E: - check_dspr2(ctx); + check_dsp_r2(ctx); switch (op2) { case OPC_MUL_PH: gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); @@ -21536,11 +21536,11 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env); break; case OPC_DPA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPAX_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPAQ_S_W_PH: @@ -21548,19 +21548,19 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPAQX_S_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPAQX_SA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPS_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPSX_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPSQ_S_W_PH: @@ -21568,11 +21568,11 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPSQX_S_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_DPSQX_SA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); break; case OPC_MULSAQ_S_W_PH: @@ -21604,7 +21604,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx,= uint32_t op1, uint32_t op2, gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env); break; case OPC_MULSA_W_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env); break; } @@ -21633,7 +21633,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx,= uint32_t op1, uint32_t op2, gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env); break; case OPC_DPA_W_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env); break; case OPC_DPAQ_S_W_QH: @@ -21653,7 +21653,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx,= uint32_t op1, uint32_t op2, gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env); break; case OPC_DPS_W_QH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env); break; case OPC_DPSQ_S_W_QH: @@ -21747,7 +21747,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx,= uint32_t op1, uint32_t op2, gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_MULQ_S_PH: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; } @@ -21971,7 +21971,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *= ctx, gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); break; case OPC_CMPGDU_EQ_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); tcg_gen_mov_tl(cpu_gpr[ret], t1); tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); @@ -21979,7 +21979,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *= ctx, tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); break; case OPC_CMPGDU_LT_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); tcg_gen_mov_tl(cpu_gpr[ret], t1); tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); @@ -21987,7 +21987,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *= ctx, tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); break; case OPC_CMPGDU_LE_QB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); tcg_gen_mov_tl(cpu_gpr[ret], t1); tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); @@ -22048,15 +22048,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env); break; case OPC_CMPGDU_EQ_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_CMPGDU_LT_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_CMPGDU_LE_OB: - check_dspr2(ctx); + check_dsp_r2(ctx); gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); break; case OPC_CMPGU_EQ_OB: @@ -22114,7 +22114,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, { TCGv t0; =20 - check_dspr2(ctx); + check_dsp_r2(ctx); =20 if (rt =3D=3D 0) { /* Treat as NOP. */ @@ -22999,7 +22999,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MULTU_G_2E: /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ - if ((ctx->insn_flags & ASE_DSPR2) && (op1 =3D=3D OPC_MULT_G_2E)) { + if ((ctx->insn_flags & ASE_DSP_R2) && (op1 =3D=3D OPC_MULT_G_2E)) { op2 =3D MASK_ADDUH_QB(ctx->opcode); switch (op2) { case OPC_ADDUH_QB: diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index d7cd4ee..acab097 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -320,7 +320,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -485,7 +485,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | + .insn_flags =3D CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3= | ASE_MT, .mmu_type =3D MMU_TYPE_R4000, }, @@ -762,7 +762,7 @@ const mips_def_t mips_defs[] =3D .mmu_type =3D MMU_TYPE_R4000, }, { - /* A generic CPU providing MIPS64 ASE DSP 2 features. + /* A generic CPU providing MIPS64 DSP R2 ASE features. FIXME: Eventually this should be replaced by a real CPU model. = */ .name =3D "mips64dspr2", .CP0_PRid =3D 0x00010000, @@ -787,7 +787,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, + .insn_flags =3D CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, .mmu_type =3D MMU_TYPE_R4000, }, =20 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363315680588.6708946597636; Fri, 12 Oct 2018 09:55:15 -0700 (PDT) Received: from localhost ([::1]:41691 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0iY-0001D9-5F for importer@patchew.org; Fri, 12 Oct 2018 12:55:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54983) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0XZ-0001AR-FU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0XW-0005B2-Ot for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46888 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0XW-000595-GU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:43:50 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 793C41A4144; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 324C61A4137; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:28 +0200 Message-Id: <1539362376-12010-21-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6 . X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Matthew Fortune Fix emulation of microMIPS R6 . instructions. Their handling was permuted. Reviewed-by: Aleksandar Markovic Signed-off-by: Matthew Fortune Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 1d31051..f76dfda 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -15197,15 +15197,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) case 0x38: /* cmovs */ switch ((ctx->opcode >> 6) & 0x7) { - case MOVN_FMT: /* SELNEZ_FMT */ + case MOVN_FMT: /* SELEQZ_FMT */ if (ctx->insn_flags & ISA_MIPS32R6) { - /* SELNEZ_FMT */ + /* SELEQZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: - gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); + gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); break; case FMT_SDPS_D: - gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); + gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); break; default: goto pool32f_invalid; @@ -15219,15 +15219,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); FINSN_3ARG_SDPS(MOVN); break; - case MOVZ_FMT: /* SELEQZ_FMT */ + case MOVZ_FMT: /* SELNEZ_FMT */ if (ctx->insn_flags & ISA_MIPS32R6) { - /* SELEQZ_FMT */ + /* SELNEZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: - gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); + gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); break; case FMT_SDPS_D: - gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); + gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); break; default: goto pool32f_invalid; --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363414498980.4629602431797; Fri, 12 Oct 2018 09:56:54 -0700 (PDT) Received: from localhost ([::1]:41703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0k7-0002Ys-Dh for importer@patchew.org; Fri, 12 Oct 2018 12:56:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KY-UR for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xg-0005Nm-Pi for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46891 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059F-F6 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7F7E81A4159; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3FA281A414D; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:29 +0200 Message-Id: <1539362376-12010-22-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 21/28] target/mips: Add opcodes for nanoMIPS EVA instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dimitrije Nikolic Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. Signed-off-by: Dimitrije Nikolic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index f76dfda..e7bc3d4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16686,6 +16686,40 @@ enum { NM_P_SC =3D 0x0b, }; =20 +/* P.LS.E0 instruction pool */ +enum { + NM_LBE =3D 0x00, + NM_SBE =3D 0x01, + NM_LBUE =3D 0x02, + NM_P_PREFE =3D 0x03, + NM_LHE =3D 0x04, + NM_SHE =3D 0x05, + NM_LHUE =3D 0x06, + NM_CACHEE =3D 0x07, + NM_LWE =3D 0x08, + NM_SWE =3D 0x09, + NM_P_LLE =3D 0x0a, + NM_P_SCE =3D 0x0b, +}; + +/* P.PREFE instruction pool */ +enum { + NM_SYNCIE =3D 0x00, + NM_PREFE =3D 0x01, +}; + +/* P.LLE instruction pool */ +enum { + NM_LLE =3D 0x00, + NM_LLWPE =3D 0x01, +}; + +/* P.SCE instruction pool */ +enum { + NM_SCE =3D 0x00, + NM_SCWPE =3D 0x01, +}; + /* P.LS.WM instruction pool */ enum { NM_LWM =3D 0x00, --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363602098247.8417172720401; Fri, 12 Oct 2018 10:00:02 -0700 (PDT) Received: from localhost ([::1]:41721 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0nA-00059T-U5 for importer@patchew.org; Fri, 12 Oct 2018 13:00:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KU-UK for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xg-0005Na-NQ for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46890 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059E-EU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8C45A1A4137; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4DE061A414F; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:30 +0200 Message-Id: <1539362376-12010-23-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add field corresponding to CP0 Config2 to DisasContext. This is needed for availability control via Config2 bits. Signed-off-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e7bc3d4..9e4aae5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1449,6 +1449,7 @@ typedef struct DisasContext { uint32_t opcode; int insn_flags; int32_t CP0_Config1; + int32_t CP0_Config2; int32_t CP0_Config3; int32_t CP0_Config5; /* Routine used to access memory */ @@ -25517,6 +25518,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->saved_pc =3D -1; ctx->insn_flags =3D env->insn_flags; ctx->CP0_Config1 =3D env->CP0_Config1; + ctx->CP0_Config2 =3D env->CP0_Config2; ctx->CP0_Config3 =3D env->CP0_Config3; ctx->CP0_Config5 =3D env->CP0_Config5; ctx->btarget =3D 0; --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363808691925.1964903095379; Fri, 12 Oct 2018 10:03:28 -0700 (PDT) Received: from localhost ([::1]:41745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0qV-0007ci-7k for importer@patchew.org; Fri, 12 Oct 2018 13:03:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001Ka-UN for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005ON-8j for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46893 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059f-No for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9F84A1A414F; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 598961A4131; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:31 +0200 Message-Id: <1539362376-12010-24-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 23/28] target/mips: Implement emulation of nanoMIPS EVA instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dimitrije Nikolic Implement emulation of nanoMIPS EVA instructions. They are all part of P.LS.E0 instruction pool, or one of its subpools. Signed-off-by: Dimitrije Nikolic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 128 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 128 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e4aae5..7ef8ef0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1992,6 +1992,35 @@ static inline void check_nms(DisasContext *ctx) } } =20 +/* + * This code generates a "reserved instruction" exception if the + * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL, + * Config2 TL, and Config5 L2C are unset. + */ +static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) +{ + if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) && + !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && + !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && + !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && + !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) + { + generate_exception_end(ctx, EXCP_RI); + } +} + +/* + * This code generates a "reserved instruction" exception if the + * Config5 EVA bit is NOT set. + */ +static inline void check_eva(DisasContext *ctx) +{ + if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) { + generate_exception_end(ctx, EXCP_RI); + } +} + =20 /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing @@ -20217,6 +20246,105 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) break; } break; + case NM_P_LS_E0: + switch (extract32(ctx->opcode, 11, 4)) { + case NM_LBE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LBE, rt, rs, s); + break; + case NM_SBE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_st(ctx, OPC_SBE, rt, rs, s); + break; + case NM_LBUE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LBUE, rt, rs, s); + break; + case NM_P_PREFE: + if (rt =3D=3D 31) { + /* case NM_SYNCIE */ + check_eva(ctx); + check_cp0_enabled(ctx); + /* Break the TB to be able to sync copied instruct= ions + immediately */ + ctx->base.is_jmp =3D DISAS_STOP; + } else { + /* case NM_PREFE */ + check_eva(ctx); + check_cp0_enabled(ctx); + /* Treat as NOP. */ + } + break; + case NM_LHE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LHE, rt, rs, s); + break; + case NM_SHE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_st(ctx, OPC_SHE, rt, rs, s); + break; + case NM_LHUE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LHUE, rt, rs, s); + break; + case NM_CACHEE: + check_nms_dl_il_sl_tl_l2c(ctx); + gen_cache_operation(ctx, rt, rs, s); + break; + case NM_LWE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LWE, rt, rs, s); + break; + case NM_SWE: + check_eva(ctx); + check_cp0_enabled(ctx); + gen_st(ctx, OPC_SWE, rt, rs, s); + break; + case NM_P_LLE: + switch (extract32(ctx->opcode, 2, 2)) { + case NM_LLE: + check_xnp(ctx); + check_eva(ctx); + check_cp0_enabled(ctx); + gen_ld(ctx, OPC_LLE, rt, rs, s); + break; + case NM_LLWPE: + check_xnp(ctx); + check_eva(ctx); + check_cp0_enabled(ctx); + gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_SCE: + switch (extract32(ctx->opcode, 2, 2)) { + case NM_SCE: + check_xnp(ctx); + check_eva(ctx); + check_cp0_enabled(ctx); + gen_st_cond(ctx, OPC_SCE, rt, rs, s); + break; + case NM_SCWPE: + check_xnp(ctx); + check_eva(ctx); + check_cp0_enabled(ctx); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + } + break; case NM_P_LS_WM: case NM_P_LS_UAWM: check_nms(ctx); --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363870890143.27395292814037; Fri, 12 Oct 2018 10:04:30 -0700 (PDT) Received: from localhost ([::1]:41748 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0rV-0008LQ-Ik for importer@patchew.org; Fri, 12 Oct 2018 13:04:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KT-UF for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005Os-Dv for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46895 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059r-Rl for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B09621A415F; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 65DA81A4152; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:32 +0200 Message-Id: <1539362376-12010-25-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 24/28] hw/mips: Update ITU to utilise SAARI/SAAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update the ITU to utilise SAARI/SAAR registers and add new ITU Control Register (ICR0). Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- hw/mips/cps.c | 8 ++++++ hw/misc/mips_itu.c | 72 +++++++++++++++++++++++++++++++++++++++++-= ---- include/hw/misc/mips_itu.h | 7 +++++ target/mips/cpu.h | 5 ++++ target/mips/op_helper.c | 14 +++++++++ 5 files changed, 99 insertions(+), 7 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4285d19..dd68795 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) Error *err =3D NULL; target_ulong gcr_base; bool itu_present =3D false; + bool saar_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { cpu =3D MIPS_CPU(cpu_create(s->cpu_type)); @@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) itu_present =3D true; /* Attach ITC Tag to the VP */ env->itc_tag =3D mips_itu_get_tag_region(&s->itu); + env->itu =3D &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } =20 cpu =3D MIPS_CPU(first_cpu); env =3D &cpu->env; + saar_present =3D (bool) env->saarp; =20 /* Inter-Thread Communication Unit */ if (itu_present) { @@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **e= rrp) =20 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &er= r); + object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", + &err); + if (saar_present) { + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_= SAAR); + } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 43bbec4..746e0c2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -55,9 +55,17 @@ typedef enum ITCView { ITCVIEW_EF_SYNC =3D 2, ITCVIEW_EF_TRY =3D 3, ITCVIEW_PV_SYNC =3D 4, - ITCVIEW_PV_TRY =3D 5 + ITCVIEW_PV_TRY =3D 5, + ITCVIEW_PV_ICR =3D 15 } ITCView; =20 +#define ITC_ICR0_CELL_NUM 16 +#define ITC_ICR0_BLK_GRAIN 8 +#define ITC_ICR0_BLK_GRAIN_MASK 0x7 +#define ITC_ICR0_ERR_AXI 2 +#define ITC_ICR0_ERR_PARITY 1 +#define ITC_ICR0_ERR_EXEC 0 + MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) { return &itu->tag_io; @@ -76,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, u= nsigned size) return tag->ITCAddressMap[index]; } =20 -static void itc_reconfigure(MIPSITUState *tag) +void itc_reconfigure(MIPSITUState *tag) { uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; @@ -84,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 + if (tag->saar_present) { + address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; + size =3D 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f); + is_enabled =3D *(uint64_t *) tag->saar & 1; + } + memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -142,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + if (s->saar_present) { + return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & + ITC_ICR0_BLK_GRAIN_MASK); + } else { + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + } } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -356,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c) view_pv_common_write(c); } =20 +static void raise_exception(int excp) +{ + current_cpu->exception_index =3D excp; + cpu_loop_exit(current_cpu); +} + static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) { MIPSITUState *s =3D (MIPSITUState *)opaque; @@ -363,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr = addr, unsigned size) ITCView view =3D get_itc_view(addr); uint64_t ret =3D -1; =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return 0; + } + switch (view) { case ITCVIEW_BYPASS: ret =3D view_bypass_read(cell); @@ -382,6 +415,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr a= ddr, unsigned size) case ITCVIEW_PV_TRY: ret =3D view_pv_try_read(cell); break; + case ITCVIEW_PV_ICR: + ret =3D s->icr0; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_read: Bad ITC View %d\n", (int)view); @@ -398,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, ITCStorageCell *cell =3D get_cell(s, addr); ITCView view =3D get_itc_view(addr); =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return; + } + switch (view) { case ITCVIEW_BYPASS: view_bypass_write(cell, data); @@ -417,6 +461,15 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, case ITCVIEW_PV_TRY: view_pv_try_write(cell); break; + case ITCVIEW_PV_ICR: + if (data & 0x7) { + /* clear ERROR bits */ + s->icr0 &=3D ~(data & 0x7); + } + /* set BLK_GRAIN */ + s->icr0 &=3D ~0x700; + s->icr0 |=3D data & 0x700; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_write: Bad ITC View %d\n", (int)view); @@ -479,10 +532,15 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D - ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | - (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + if (s->saar_present) { + *(uint64_t *) s->saar =3D 0x11 << 1; + s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; + } else { + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D + ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | + (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + } itc_reconfigure(s); =20 itc_reset_cells(s); diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 030eb4a..bb9667a 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -66,6 +66,13 @@ typedef struct MIPSITUState { /* ITC Configuration Tags */ uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM]; MemoryRegion tag_io; + + /* ITU Control Registers */ + uint64_t icr0; + + /* SAAR */ + bool saar_present; + void *saar; } MIPSITUState; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f07b94e..9c57878 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -172,6 +172,7 @@ struct TCState { float_status msa_fp_status; }; =20 +struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; @@ -658,6 +659,7 @@ struct CPUMIPSState { const mips_def_t *cpu_model; void *irq[8]; QEMUTimer *timer; /* Internal timer */ + struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ }; @@ -800,6 +802,9 @@ void cpu_set_exception_base(int vp_index, target_ulong = address); /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); =20 +/* mips_itu.c */ +void itc_reconfigure(struct MIPSITUState *tag); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 1fae357..2ef0134 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1618,6 +1618,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) uint32_t target =3D env->CP0_SAARI & 0x3f; if (target < 2) { env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 @@ -1628,6 +1635,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) env->CP0_SAAR[target] =3D (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363894656524.8033508526102; Fri, 12 Oct 2018 10:04:54 -0700 (PDT) Received: from localhost ([::1]:41751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0rt-0000DQ-9b for importer@patchew.org; Fri, 12 Oct 2018 13:04:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001Kb-US for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005On-Bz for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46892 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059h-RB for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B035E1A415C; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 74BE91A4157; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:33 +0200 Message-Id: <1539362376-12010-26-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 25/28] hw/mips: Add Data Scratch Pad RAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch pad RAM used for temporary storage of data. The DSPRAM provides a connection to on-chip memory or memory-mapped registers, which are accessed in parallel with the L1 data cache to minimize access latency. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- default-configs/mips-softmmu-common.mak | 1 + hw/mips/cps.c | 3 ++- hw/mips/mips_malta.c | 31 +++++++++++++++++++++++++++++= ++ hw/misc/Makefile.objs | 1 + include/hw/mips/cps.h | 2 ++ target/mips/cpu.h | 5 +++++ target/mips/internal.h | 1 + target/mips/op_helper.c | 10 ++++++++++ target/mips/translate.c | 7 +++++++ 9 files changed, 60 insertions(+), 1 deletion(-) diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips= -softmmu-common.mak index fae2347..45f2cbf 100644 --- a/default-configs/mips-softmmu-common.mak +++ b/default-configs/mips-softmmu-common.mak @@ -36,3 +36,4 @@ CONFIG_EMPTY_SLOT=3Dy CONFIG_MIPS_CPS=3Dy CONFIG_MIPS_ITU=3Dy CONFIG_I2C=3Dy +CONFIG_MIPS_DSPRAM=3Dy diff --git a/hw/mips/cps.c b/hw/mips/cps.c index dd68795..93d3bea 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -102,7 +102,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", &err); if (saar_present) { - qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_= SAAR); + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", + (void *) &env->CP0_SAAR[0]); } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 29b90ba..1b1bbd8 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1169,6 +1169,36 @@ static void create_cps(MaltaState *s, const char *cp= u_type, *cbus_irq =3D NULL; } =20 +static void create_dspram(void) +{ + MIPSCPU *cpu =3D MIPS_CPU(first_cpu); + CPUMIPSState *env =3D &cpu->env; + bool dspram_present =3D (bool) env->dspramp; + Error *err =3D NULL; + + env->dspram =3D g_new0(MIPSDSPRAMState, 1); + + /* DSPRAM */ + if (dspram_present) { + if (!(bool) env->saarp) { + error_report("%s: DSPRAM requires SAAR registers", __func__); + exit(1); + } + object_initialize(env->dspram, sizeof(MIPSDSPRAMState), + TYPE_MIPS_DSPRAM); + qdev_set_parent_bus(DEVICE(env->dspram), sysbus_get_default()); + qdev_prop_set_ptr(DEVICE(env->dspram), "saar", + (void *) &env->CP0_SAAR[1]); + object_property_set_bool(OBJECT(env->dspram), true, "realized", &e= rr); + if (err !=3D NULL) { + error_report("%s: DSPRAM initialisation failed", __func__); + exit(1); + } + memory_region_add_subregion(get_system_memory(), 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(env->dspram), 0)= ); + } +} + static void mips_create_cpu(MaltaState *s, const char *cpu_type, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { @@ -1177,6 +1207,7 @@ static void mips_create_cpu(MaltaState *s, const char= *cpu_type, } else { create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq); } + create_dspram(); } =20 static diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 6d50b03..37a1b41 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o obj-$(CONFIG_MIPS_ITU) +=3D mips_itu.o +obj-$(CONFIG_MIPS_DSPRAM) +=3D mips_dspram.o obj-$(CONFIG_MPS2_FPGAIO) +=3D mps2-fpgaio.o obj-$(CONFIG_MPS2_SCC) +=3D mps2-scc.o =20 diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index aab1af9..a637036 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -25,6 +25,7 @@ #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" #include "hw/misc/mips_itu.h" +#include "hw/misc/mips_dspram.h" =20 #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -41,6 +42,7 @@ typedef struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + MIPSDSPRAMState dspram; } MIPSCPSState; =20 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c57878..a2aca3f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -644,6 +644,7 @@ struct CPUMIPSState { uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ int insn_flags; /* Supported instruction set */ int saarp; + int dspramp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -661,6 +662,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ + struct MIPSDSPRAMState *dspram; target_ulong exception_base; /* ExceptionBase input to the core */ }; =20 @@ -805,6 +807,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int = level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); =20 +/* mips_dspram.c */ +void dspram_reconfigure(struct MIPSDSPRAMState *dspram); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index 6cf00d8..6aedf70 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -62,6 +62,7 @@ struct mips_def_t { int insn_flags; enum mips_mmu_types mmu_type; int32_t SAARP; + int32_t DSPRAMP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 2ef0134..31fba8b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1624,6 +1624,11 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } @@ -1641,6 +1646,11 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } diff --git a/target/mips/translate.c b/target/mips/translate.c index 7ef8ef0..03ba797 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26037,6 +26037,7 @@ void cpu_state_reset(CPUMIPSState *env) env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; env->saarp =3D env->cpu_model->SAARP; + env->dspramp =3D env->cpu_model->DSPRAMP; =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); @@ -26191,6 +26192,12 @@ void cpu_state_reset(CPUMIPSState *env) msa_reset(env); } =20 + /* DSPRAM */ + if (env->dspramp) { + /* Fixed DSPRAM size with Default Value */ + env->CP0_SAAR[1] =3D 0x10 << 1; + } + compute_hflags(env); restore_fp_status(env); restore_pamask(env); --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363488611836.8201207357487; Fri, 12 Oct 2018 09:58:08 -0700 (PDT) Received: from localhost ([::1]:41709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0lL-0003Z9-Cf for importer@patchew.org; Fri, 12 Oct 2018 12:58:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KX-US for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005Od-AU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46894 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xg-00059o-SO for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BA4BB1A4131; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 851B41A4150; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:34 +0200 Message-Id: <1539362376-12010-27-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 26/28] target/mips: Add DEC feature to mips32r6-generic CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Set Config5.DEC Dual Endian Capability bit of mips32r6-generic CPU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/translate_init.inc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index acab097..4c62c50 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -428,7 +428,8 @@ const mips_def_t mips_defs[] =3D (1 << CP0C3_RXI) | (1U << CP0C3_M), .CP0_Config4 =3D MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), - .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB= ), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_DEC= ) | + (1 << CP0C5_LLB), .CP0_Config5_rw_bitmask =3D (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask =3D 0, --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363690978665.4509434157904; Fri, 12 Oct 2018 10:01:30 -0700 (PDT) Received: from localhost ([::1]:41733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0ob-0006GK-Ps for importer@patchew.org; Fri, 12 Oct 2018 13:01:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KW-Uc for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005PC-IU for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46896 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xh-0005A9-7R for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C49301A414D; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 922FB1A4153; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:35 +0200 Message-Id: <1539362376-12010-28-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 27/28] target/mips: Add MSA ASE to MIPS64R2-generic CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add MSA ASE to MIPS64R2-generic CPU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/translate_init.inc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index 4c62c50..38c847f 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -620,7 +620,10 @@ const mips_def_t mips_defs[] =3D (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA)= | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_MSA= P), + .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M), + .CP0_Config4_rw_bitmask =3D 0, + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn), .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 0, .SYNCI_Step =3D 32, @@ -634,7 +637,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64R2 | ASE_MIPS3D, + .insn_flags =3D CPU_MIPS64R2 | ASE_MIPS3D | ASE_MSA, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.7.4 From nobody Fri May 17 05:50:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539363660729987.3405891938057; Fri, 12 Oct 2018 10:01:00 -0700 (PDT) Received: from localhost ([::1]:41727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0o7-0005xN-2Q for importer@patchew.org; Fri, 12 Oct 2018 13:00:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB0Xk-0001KV-UF for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB0Xh-0005Pe-NY for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46897 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB0Xh-0005AB-9g for qemu-devel@nongnu.org; Fri, 12 Oct 2018 12:44:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CE1DA1A4150; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9FD4F1A415B; Fri, 12 Oct 2018 18:43:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 18:39:36 +0200 Message-Id: <1539362376-12010-29-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539362376-12010-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 28/28] target/mips: Add I6500 core configuration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add I6500 core configuration. Note that this configuration is supported only by best-effort due to lack of certain features in QEMU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/translate_init.inc.c | 43 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index 38c847f..b25a857 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -726,6 +726,49 @@ const mips_def_t mips_defs[] =3D .mmu_type =3D MMU_TYPE_R4000, }, { + .name =3D "I6500", + .CP0_PRid =3D 0x1B000, + .CP0_Config0 =3D MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_= AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA)= | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA)= | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULR= I) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_V= Int), + .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_ULS) | (1 << CP0C5_CRC= P) | + (3 << CP0C5_GI) | (0 << CP0C5_XNP) | (1 << CP0C5_VP= ) | + (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | (1 << CP0C5_M= RP), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_MI) | + (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 0, + .SYNCI_Step =3D 64, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x30D8FFFF, + .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask =3D (1 << CP0PG_ELPA), + .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV= ), + .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask =3D 0x0103FFFF, + .MSAIR =3D 0x03 << MSAIR_ProcID, + .SEGBITS =3D 48, + .PABITS =3D 48, + .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .mmu_type =3D MMU_TYPE_R4000, + .SAARP =3D 1, + .DSPRAMP =3D 1, + }, + { .name =3D "Loongson-2E", .CP0_PRid =3D 0x6302, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ --=20 2.7.4