From nobody Tue Feb 10 02:45:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539257275761723.6933803777866; Thu, 11 Oct 2018 04:27:55 -0700 (PDT) Received: from localhost ([::1]:33581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZ88-0008JZ-3g for importer@patchew.org; Thu, 11 Oct 2018 07:27:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZ4V-0005XD-ET for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:24:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAZ4R-0007MW-La for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:24:01 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:53489 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAZ4N-0007L6-UM for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:23:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 60BC61A1E95; Thu, 11 Oct 2018 13:23:52 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3EE581A1DF0; Thu, 11 Oct 2018 13:23:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:22:10 +0200 Message-Id: <1539256947-22807-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic --- target/mips/cpu.h | 6 ++++++ target/mips/helper.h | 1 + target/mips/machine.c | 1 + target/mips/op_helper.c | 34 ++++++++++++++++++++++++++++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 5 files changed, 62 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c8999a8..01cd65c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -290,6 +290,12 @@ struct CPUMIPSState { #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_M= ASK) target_ulong CP0_PWBase; + target_ulong CP0_PWField; +#define CP0PF_GDI 24 /* 29..24 */ +#define CP0PF_UDI 18 /* 23..18 */ +#define CP0PF_MDI 12 /* 17..12 */ +#define CP0PF_PTI 6 /* 11..6 */ +#define CP0PF_PTEI 0 /* 5..0 */ int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; diff --git a/target/mips/helper.h b/target/mips/helper.h index b2a780a..6366f9b 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -120,6 +120,7 @@ DEF_HELPER_2(mtc0_pagegrain, void, env, tl) DEF_HELPER_2(mtc0_segctl0, void, env, tl) DEF_HELPER_2(mtc0_segctl1, void, env, tl) DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) DEF_HELPER_2(mtc0_wired, void, env, tl) DEF_HELPER_2(mtc0_srsconf0, void, env, tl) DEF_HELPER_2(mtc0_srsconf1, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 86702c6..aa6ef56 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -257,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), + VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), VMSTATE_INT32(env.CP0_Wired, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c148b31..bc506de 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1445,6 +1445,40 @@ void helper_mtc0_segctl2(CPUMIPSState *env, target_u= long arg1) tlb_flush(cs); } =20 +void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) +{ +#ifdef TARGET_MIPS64 + env->CP0_PWField =3D arg1 & 0x3F3FFFFFFFULL; +#else + uint32_t mask =3D 0x3FFFFFFF; + uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3F; + uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3F; + + if ((env->insn_flags & ISA_MIPS32R6)) { + if (((arg1 >> CP0PF_GDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_GDI); + } + if (((arg1 >> CP0PF_UDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_UDI); + } + if (((arg1 >> CP0PF_MDI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_MDI); + } + if (((arg1 >> CP0PF_PTI) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_PTI); + } + } + env->CP0_PWField =3D arg1 & mask; + + if ((new_ptei >=3D 32) || + ((env->insn_flags & ISA_MIPS32R6) && + (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { + env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | + (old_ptei << CP0PF_PTEI); + } +#endif +} + void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 7af9a21..882a765 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5553,6 +5553,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -6259,6 +6264,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwfield(cpu_env, arg); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -6974,6 +6984,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } @@ -7662,6 +7677,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); rn =3D "PWBase"; break; + case 6: + check_pw(ctx); + gen_helper_mtc0_pwfield(cpu_env, arg); + rn =3D "PWField"; + break; default: goto cp0_unimplemented; } --=20 2.7.4