From nobody Thu Nov 6 06:28:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539257745089477.22146151573327; Thu, 11 Oct 2018 04:35:45 -0700 (PDT) Received: from localhost ([::1]:33620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZFn-0006EF-SG for importer@patchew.org; Thu, 11 Oct 2018 07:35:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZ6S-0007FO-1k for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:26:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAZ6N-0008FE-EE for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:26:03 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60968 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAZ6M-0008EK-WF for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:25:59 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 582C21A2053; Thu, 11 Oct 2018 13:25:57 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 33FA11A1FF2; Thu, 11 Oct 2018 13:25:57 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:22:24 +0200 Message-Id: <1539256947-22807-20-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch pad RAM used for temporary storage of data. The DSPRAM provides a connection to on-chip memory or memory-mapped registers, which are accessed in parallel with the L1 data cache to minimize access latency. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- default-configs/mips-softmmu-common.mak | 1 + hw/mips/cps.c | 3 ++- hw/mips/mips_malta.c | 31 +++++++++++++++++++++++++++++= ++ hw/misc/Makefile.objs | 1 + include/hw/mips/cps.h | 2 ++ target/mips/cpu.h | 5 +++++ target/mips/internal.h | 1 + target/mips/op_helper.c | 10 ++++++++++ target/mips/translate.c | 7 +++++++ 9 files changed, 60 insertions(+), 1 deletion(-) diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips= -softmmu-common.mak index fae2347..45f2cbf 100644 --- a/default-configs/mips-softmmu-common.mak +++ b/default-configs/mips-softmmu-common.mak @@ -36,3 +36,4 @@ CONFIG_EMPTY_SLOT=3Dy CONFIG_MIPS_CPS=3Dy CONFIG_MIPS_ITU=3Dy CONFIG_I2C=3Dy +CONFIG_MIPS_DSPRAM=3Dy diff --git a/hw/mips/cps.c b/hw/mips/cps.c index dd68795..93d3bea 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -102,7 +102,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", &err); if (saar_present) { - qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_= SAAR); + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", + (void *) &env->CP0_SAAR[0]); } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 29b90ba..1b1bbd8 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1169,6 +1169,36 @@ static void create_cps(MaltaState *s, const char *cp= u_type, *cbus_irq =3D NULL; } =20 +static void create_dspram(void) +{ + MIPSCPU *cpu =3D MIPS_CPU(first_cpu); + CPUMIPSState *env =3D &cpu->env; + bool dspram_present =3D (bool) env->dspramp; + Error *err =3D NULL; + + env->dspram =3D g_new0(MIPSDSPRAMState, 1); + + /* DSPRAM */ + if (dspram_present) { + if (!(bool) env->saarp) { + error_report("%s: DSPRAM requires SAAR registers", __func__); + exit(1); + } + object_initialize(env->dspram, sizeof(MIPSDSPRAMState), + TYPE_MIPS_DSPRAM); + qdev_set_parent_bus(DEVICE(env->dspram), sysbus_get_default()); + qdev_prop_set_ptr(DEVICE(env->dspram), "saar", + (void *) &env->CP0_SAAR[1]); + object_property_set_bool(OBJECT(env->dspram), true, "realized", &e= rr); + if (err !=3D NULL) { + error_report("%s: DSPRAM initialisation failed", __func__); + exit(1); + } + memory_region_add_subregion(get_system_memory(), 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(env->dspram), 0)= ); + } +} + static void mips_create_cpu(MaltaState *s, const char *cpu_type, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { @@ -1177,6 +1207,7 @@ static void mips_create_cpu(MaltaState *s, const char= *cpu_type, } else { create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq); } + create_dspram(); } =20 static diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 6d50b03..37a1b41 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o obj-$(CONFIG_MIPS_ITU) +=3D mips_itu.o +obj-$(CONFIG_MIPS_DSPRAM) +=3D mips_dspram.o obj-$(CONFIG_MPS2_FPGAIO) +=3D mps2-fpgaio.o obj-$(CONFIG_MPS2_SCC) +=3D mps2-scc.o =20 diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index aab1af9..a637036 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -25,6 +25,7 @@ #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" #include "hw/misc/mips_itu.h" +#include "hw/misc/mips_dspram.h" =20 #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -41,6 +42,7 @@ typedef struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + MIPSDSPRAMState dspram; } MIPSCPSState; =20 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c57878..a2aca3f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -644,6 +644,7 @@ struct CPUMIPSState { uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ int insn_flags; /* Supported instruction set */ int saarp; + int dspramp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -661,6 +662,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ + struct MIPSDSPRAMState *dspram; target_ulong exception_base; /* ExceptionBase input to the core */ }; =20 @@ -805,6 +807,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int = level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); =20 +/* mips_dspram.c */ +void dspram_reconfigure(struct MIPSDSPRAMState *dspram); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index 6cf00d8..6aedf70 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -62,6 +62,7 @@ struct mips_def_t { int insn_flags; enum mips_mmu_types mmu_type; int32_t SAARP; + int32_t DSPRAMP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 2ef0134..31fba8b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1624,6 +1624,11 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } @@ -1641,6 +1646,11 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } diff --git a/target/mips/translate.c b/target/mips/translate.c index f631930..608b276 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25986,6 +25986,7 @@ void cpu_state_reset(CPUMIPSState *env) env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; env->saarp =3D env->cpu_model->SAARP; + env->dspramp =3D env->cpu_model->DSPRAMP; =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); @@ -26122,6 +26123,12 @@ void cpu_state_reset(CPUMIPSState *env) msa_reset(env); } =20 + /* DSPRAM */ + if (env->dspramp) { + /* Fixed DSPRAM size with Default Value */ + env->CP0_SAAR[1] =3D 0x10 << 1; + } + compute_hflags(env); restore_fp_status(env); restore_pamask(env); --=20 2.7.4