From nobody Tue Feb 10 07:42:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539257515684756.9552632262925; Thu, 11 Oct 2018 04:31:55 -0700 (PDT) Received: from localhost ([::1]:33603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZC6-0003HF-Dt for importer@patchew.org; Thu, 11 Oct 2018 07:31:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAZ56-0005xk-OO for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:24:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAZ53-0007da-TG for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:24:39 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55049 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAZ51-0007Zz-LM for qemu-devel@nongnu.org; Thu, 11 Oct 2018 07:24:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id AA80E1A1E4F; Thu, 11 Oct 2018 13:24:33 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7EF821A2045; Thu, 11 Oct 2018 13:24:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:22:14 +0200 Message-Id: <1539256947-22807-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539256947-22807-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/DMFC0 in 64-bit architectures. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/helper.h | 3 +++ target/mips/machine.c | 2 +- target/mips/op_helper.c | 23 +++++++++++++++++++++-- target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 65 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5e45e97..10c3813 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -531,7 +531,7 @@ struct CPUMIPSState { uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; - int32_t CP0_WatchHi[8]; + uint64_t CP0_WatchHi[8]; #define CP0WH_ASID 16 target_ulong CP0_XContext; int32_t CP0_Framemask; diff --git a/target/mips/helper.h b/target/mips/helper.h index c23e4e5..0ec500a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -76,6 +76,7 @@ DEF_HELPER_1(mfc0_maar, tl, env) DEF_HELPER_1(mfhc0_maar, tl, env) DEF_HELPER_2(mfc0_watchlo, tl, env, i32) DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) DEF_HELPER_1(mfc0_debug, tl, env) DEF_HELPER_1(mftc0_debug, tl, env) #ifdef TARGET_MIPS64 @@ -87,6 +88,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -153,6 +155,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl) DEF_HELPER_2(mtc0_maari, void, env, tl) DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) DEF_HELPER_2(mtc0_xcontext, void, env, tl) DEF_HELPER_2(mtc0_framemask, void, env, tl) DEF_HELPER_2(mtc0_debug, void, env, tl) diff --git a/target/mips/machine.c b/target/mips/machine.c index 67a85a0..0ef9b71 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -292,7 +292,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), VMSTATE_UINT64(env.lladdr, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), - VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), + VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), VMSTATE_INT32(env.CP0_Debug, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index af130f6..3d86c60 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -991,7 +991,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, ui= nt32_t sel) =20 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) { - return env->CP0_WatchHi[sel]; + return (int32_t) env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel] >> 32; } =20 target_ulong helper_mfc0_debug(CPUMIPSState *env) @@ -1059,6 +1064,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env,= uint32_t sel) { return env->CP0_WatchLo[sel]; } + +target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1818,11 +1828,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_= ulong arg1, uint32_t sel) =20 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) { - int mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + uint64_t mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_AS= ID); + if ((env->CP0_Config5 >> CP0C5_MI) & 1) { + mask |=3D 0xFFFFFFFF00000000ULL; /* MMID */ + } env->CP0_WatchHi[sel] =3D arg1 & mask; env->CP0_WatchHi[sel] &=3D ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } =20 +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t s= el) +{ + env->CP0_WatchHi[sel] =3D ((uint64_t) (arg1) << 32) | + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL= ); +} + void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) { target_ulong mask =3D (1ULL << (env->SEGBITS - 7)) - 1; diff --git a/target/mips/translate.c b/target/mips/translate.c index f669d48..8bff0e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5223,6 +5223,25 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 19: + switch (sel) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* upper 32 bits are only available when Config5MI !=3D 0 */ + /* CP0_CHECK(ctx->mi); */ + gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel])= , 0); + rn =3D "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case 28: switch (sel) { case 0: @@ -5295,6 +5314,25 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case 19: + switch (sel) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* upper 32 bits are only available when Config5MI !=3D 0 */ + /* CP0_CHECK(ctx->mi); */ + gen_helper_0e1i(mthc0_watchhi, arg, sel); + rn =3D "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case 28: switch (sel) { case 0: @@ -7293,7 +7331,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 6: case 7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); - gen_helper_1e0i(mfc0_watchhi, arg, sel); + gen_helper_1e0i(dmfc0_watchhi, arg, sel); rn =3D "WatchHi"; break; default: --=20 2.7.4