From nobody Thu Nov 6 03:30:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15390115076881016.8961100606311; Mon, 8 Oct 2018 08:11:47 -0700 (PDT) Received: from localhost ([::1]:46813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9XCE-0005XH-Gu for importer@patchew.org; Mon, 08 Oct 2018 11:11:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9X0Y-0005FC-6h for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:59:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9X0X-0006N9-C7 for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:59:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45945 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9X0X-0006MK-0M for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:59:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D2F611A1FB8; Mon, 8 Oct 2018 16:59:39 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id B3EB41A1E69; Mon, 8 Oct 2018 16:59:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 16:56:31 +0200 Message-Id: <1539010596-30858-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539010596-30858-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539010596-30858-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v3 07/12] target/mips: Implement emulation of nanoMIPS EVA instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dimitrije Nikolic Implement emulation of nanoMIPS EVA instructions. They are all part of P.LS.E0 instruction pool, or one of its subpools. Signed-off-by: Dimitrije Nikolic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7b1a6b1..d872fa7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1979,6 +1979,17 @@ static inline void check_nms(DisasContext *ctx) } } =20 +/* + * This code generates a "reserved instruction" exception if the + * Config5 EVA bit is NOT set. + */ +static inline void check_eva(DisasContext *ctx) +{ + if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) { + generate_exception_end(ctx, EXCP_RI); + } +} + =20 /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing @@ -20029,6 +20040,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) break; } break; + case NM_P_LS_E0: + check_eva(ctx); + switch (extract32(ctx->opcode, 11, 4)) { + case NM_LBE: + gen_ld(ctx, OPC_LBE, rt, rs, s); + break; + case NM_SBE: + gen_st(ctx, OPC_SBE, rt, rs, s); + break; + case NM_LBUE: + gen_ld(ctx, OPC_LBUE, rt, rs, s); + break; + case NM_P_PREFE: + if (rt =3D=3D 31) { + /* SYNCIE */ + /* Break the TB to be able to sync copied instruct= ions + immediately */ + ctx->base.is_jmp =3D DISAS_STOP; + } else { + /* PREF */ + /* Treat as NOP. */ + } + break; + case NM_LHE: + gen_ld(ctx, OPC_LHE, rt, rs, s); + break; + case NM_SHE: + gen_st(ctx, OPC_SHE, rt, rs, s); + break; + case NM_LHUE: + gen_ld(ctx, OPC_LHUE, rt, rs, s); + break; + case NM_CACHEE: + /* Treat as no-op */ + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { + gen_cache_operation(ctx, rt, rs, s); + } + break; + case NM_LWE: + gen_ld(ctx, OPC_LWE, rt, rs, s); + break; + case NM_SWE: + gen_st(ctx, OPC_SWE, rt, rs, s); + break; + case NM_P_LLE: + switch (extract32(ctx->opcode, 2, 2)) { + case NM_LL: + gen_ld(ctx, OPC_LLE, rt, rs, s); + break; + case NM_LLWP: + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_SCE: + switch (extract32(ctx->opcode, 2, 2)) { + case NM_SC: + gen_st_cond(ctx, OPC_SCE, rt, rs, s); + break; + case NM_SCWP: + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + } + break; case NM_P_LS_WM: case NM_P_LS_UAWM: check_nms(ctx); --=20 2.7.4