From nobody Tue Feb 10 02:02:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539011442243788.5772655491162; Mon, 8 Oct 2018 08:10:42 -0700 (PDT) Received: from localhost ([::1]:46801 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9XBA-0004cN-Sh for importer@patchew.org; Mon, 08 Oct 2018 11:10:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46884) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9X1c-000686-8V for qemu-devel@nongnu.org; Mon, 08 Oct 2018 11:00:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9X1Z-0007A4-5N for qemu-devel@nongnu.org; Mon, 08 Oct 2018 11:00:47 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48434 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9X1Y-000755-Ly for qemu-devel@nongnu.org; Mon, 08 Oct 2018 11:00:45 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B6F561A1E5B; Mon, 8 Oct 2018 17:00:39 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 946CB1A1DDE; Mon, 8 Oct 2018 17:00:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 16:56:34 +0200 Message-Id: <1539010596-30858-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539010596-30858-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539010596-30858-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v3 10/12] hw/mips: Update ITU to utilise SAARI/SAAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update the ITU to utilise SAARI/SAAR registers and add new ITU Control Register (ICR0). Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- hw/mips/cps.c | 8 ++++++ hw/misc/mips_itu.c | 72 +++++++++++++++++++++++++++++++++++++++++-= ---- include/hw/misc/mips_itu.h | 7 +++++ target/mips/cpu.h | 5 ++++ target/mips/op_helper.c | 14 +++++++++ 5 files changed, 99 insertions(+), 7 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4285d19..dd68795 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) Error *err =3D NULL; target_ulong gcr_base; bool itu_present =3D false; + bool saar_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { cpu =3D MIPS_CPU(cpu_create(s->cpu_type)); @@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) itu_present =3D true; /* Attach ITC Tag to the VP */ env->itc_tag =3D mips_itu_get_tag_region(&s->itu); + env->itu =3D &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } =20 cpu =3D MIPS_CPU(first_cpu); env =3D &cpu->env; + saar_present =3D (bool) env->saarp; =20 /* Inter-Thread Communication Unit */ if (itu_present) { @@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **e= rrp) =20 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &er= r); + object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", + &err); + if (saar_present) { + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_= SAAR); + } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 43bbec4..746e0c2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -55,9 +55,17 @@ typedef enum ITCView { ITCVIEW_EF_SYNC =3D 2, ITCVIEW_EF_TRY =3D 3, ITCVIEW_PV_SYNC =3D 4, - ITCVIEW_PV_TRY =3D 5 + ITCVIEW_PV_TRY =3D 5, + ITCVIEW_PV_ICR =3D 15 } ITCView; =20 +#define ITC_ICR0_CELL_NUM 16 +#define ITC_ICR0_BLK_GRAIN 8 +#define ITC_ICR0_BLK_GRAIN_MASK 0x7 +#define ITC_ICR0_ERR_AXI 2 +#define ITC_ICR0_ERR_PARITY 1 +#define ITC_ICR0_ERR_EXEC 0 + MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) { return &itu->tag_io; @@ -76,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, u= nsigned size) return tag->ITCAddressMap[index]; } =20 -static void itc_reconfigure(MIPSITUState *tag) +void itc_reconfigure(MIPSITUState *tag) { uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; @@ -84,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 + if (tag->saar_present) { + address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; + size =3D 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f); + is_enabled =3D *(uint64_t *) tag->saar & 1; + } + memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -142,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + if (s->saar_present) { + return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & + ITC_ICR0_BLK_GRAIN_MASK); + } else { + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + } } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -356,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c) view_pv_common_write(c); } =20 +static void raise_exception(int excp) +{ + current_cpu->exception_index =3D excp; + cpu_loop_exit(current_cpu); +} + static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) { MIPSITUState *s =3D (MIPSITUState *)opaque; @@ -363,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr = addr, unsigned size) ITCView view =3D get_itc_view(addr); uint64_t ret =3D -1; =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return 0; + } + switch (view) { case ITCVIEW_BYPASS: ret =3D view_bypass_read(cell); @@ -382,6 +415,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr a= ddr, unsigned size) case ITCVIEW_PV_TRY: ret =3D view_pv_try_read(cell); break; + case ITCVIEW_PV_ICR: + ret =3D s->icr0; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_read: Bad ITC View %d\n", (int)view); @@ -398,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, ITCStorageCell *cell =3D get_cell(s, addr); ITCView view =3D get_itc_view(addr); =20 + switch (size) { + case 1: + case 2: + s->icr0 |=3D 1 << ITC_ICR0_ERR_AXI; + raise_exception(EXCP_DBE); + return; + } + switch (view) { case ITCVIEW_BYPASS: view_bypass_write(cell, data); @@ -417,6 +461,15 @@ static void itc_storage_write(void *opaque, hwaddr add= r, uint64_t data, case ITCVIEW_PV_TRY: view_pv_try_write(cell); break; + case ITCVIEW_PV_ICR: + if (data & 0x7) { + /* clear ERROR bits */ + s->icr0 &=3D ~(data & 0x7); + } + /* set BLK_GRAIN */ + s->icr0 &=3D ~0x700; + s->icr0 |=3D data & 0x700; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_write: Bad ITC View %d\n", (int)view); @@ -479,10 +532,15 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D - ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | - (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + if (s->saar_present) { + *(uint64_t *) s->saar =3D 0x11 << 1; + s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; + } else { + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D + ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | + (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + } itc_reconfigure(s); =20 itc_reset_cells(s); diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 030eb4a..bb9667a 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -66,6 +66,13 @@ typedef struct MIPSITUState { /* ITC Configuration Tags */ uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM]; MemoryRegion tag_io; + + /* ITU Control Registers */ + uint64_t icr0; + + /* SAAR */ + bool saar_present; + void *saar; } MIPSITUState; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 87c0a93..7bc45d5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -172,6 +172,7 @@ struct TCState { float_status msa_fp_status; }; =20 +struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; @@ -639,6 +640,7 @@ struct CPUMIPSState { const mips_def_t *cpu_model; void *irq[8]; QEMUTimer *timer; /* Internal timer */ + struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ }; @@ -781,6 +783,9 @@ void cpu_set_exception_base(int vp_index, target_ulong = address); /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); =20 +/* mips_itu.c */ +void itc_reconfigure(struct MIPSITUState *tag); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 6f53757..eb63d20 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1560,6 +1560,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) uint32_t target =3D env->CP0_SAARI & 0x3f; if (target < 2) { env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 @@ -1570,6 +1577,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) env->CP0_SAAR[target] =3D (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 --=20 2.7.4