From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579579092397.6789010970472; Wed, 3 Oct 2018 08:12:59 -0700 (PDT) Received: from localhost ([::1]:49236 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7ipd-0000Gh-Sr for importer@patchew.org; Wed, 03 Oct 2018 11:12:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7iln-00046W-41 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:09:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7ilk-000400-1U for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:08:59 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:41309) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7ilj-0003zq-RE; Wed, 03 Oct 2018 11:08:55 -0400 Received: by mail-pf1-x442.google.com with SMTP id m77-v6so1824450pfi.8; Wed, 03 Oct 2018 08:08:55 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id k71-v6sm2779490pge.44.2018.10.03.08.08.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XNRrhUSKw6Our9SaiQsbulGGdRPGI+Mkwoe40VigXv0=; b=JIutbVJruEuO8tZweWmNwRVDgthLF8wT+j/mwVexkmnQTnsevhQTADjtpuvG2Rq3pE uZjwaB1iFU7VsoRAUjcxSvW3LTKiRgUqb7YaGQU+sfnEJdBkvDb9UxmmP6QbKVqc0D6D N7NQOhOczAmVI03qnGaojr3TZWwasSCQcuIzBJn49jQCoLB2IWf2VXo7ItEEqMdPdIHS id80EqCfue3uz0HoT/UZ5+sK9ieW8zFyIylBzuOh+CxyMzlFjSCmwNJsrwEsqwMAeVPE Iqkt5tb9ei+LvopQuNZueXikk6dq+gTdZ2xy9/pRwOgLdUjCY1cwlvN+FKq7a0ce/PTX 9P/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XNRrhUSKw6Our9SaiQsbulGGdRPGI+Mkwoe40VigXv0=; b=TZmnu8cMWQ9zUEERqwHMs5+zrU1o/3cCOdrd137fjYqnUr+a98iiiaM/RW68cu0Pb6 Q0PGjCGhgHYv3Jfh4NQMjJvR5p/RQuS/2tLz0pmbYvMToCx53dO8FmWcDZ/C2lA0zJF4 JLry4EF8x4ujz/yuSIHZos0tPP7lRM+My/HHemZDXqYLO29SEz7Tom1/97RfTAyPF1f5 6zx3aAcb9syA4PGfeugh1S1e3+KJ7R50JNnoVBNRgwPGNNsz1VjdDbpxO0YeLu7ELaWY Gv/VN0szduOJL9xdq620utgd4WQKK0aU820MAJpngKAHf8jUWCxawf189biSjb1vto95 T2IQ== X-Gm-Message-State: ABuFfojIEM2U9Co+h/CrDJVqK0R2jJR7vKT44oXapnq4y3ZVPIQLytb6 QFWX4u8n0XSOy/BQMgpGAuoic8eadPo= X-Google-Smtp-Source: ACcGV63bL54hgixKn+wifiGYNw63Niw5bfDdXMvMk/Bs9M6mnZ8jdvslXg9C6rDEVu+eOsBXnuDf2g== X-Received: by 2002:a62:3541:: with SMTP id c62-v6mr2055150pfa.45.1538579334373; Wed, 03 Oct 2018 08:08:54 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:35 +0700 Message-Id: <1538579266-8389-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v1 01/12] net: cadence_gem: Disable TSU feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Disable the Timestamping Unit feature bit since QEMU does not yet support it. This allows guest SW to correctly probe for its existance. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 0fa4b0d..e560b7a 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1228,7 +1228,7 @@ static void gem_reset(DeviceState *d) s->regs[GEM_MODID] =3D s->revision; s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; - s->regs[GEM_DESCONF5] =3D 0x002f2145; + s->regs[GEM_DESCONF5] =3D 0x002f2045; s->regs[GEM_DESCONF6] =3D 0x00000200; =20 /* Set MAC address */ --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579489716298.7469304596765; Wed, 3 Oct 2018 08:11:29 -0700 (PDT) Received: from localhost ([::1]:49228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7ioA-0006iZ-1i for importer@patchew.org; Wed, 03 Oct 2018 11:11:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47592) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7imL-0004ZU-Mq for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:09:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7imI-0004Ql-K5 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:09:33 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:40039) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7imI-0004QJ-CK; Wed, 03 Oct 2018 11:09:30 -0400 Received: by mail-pg1-x544.google.com with SMTP id n31-v6so1705400pgm.7; Wed, 03 Oct 2018 08:09:30 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id v189-v6sm3868926pfb.54.2018.10.03.08.09.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:09:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/QSgLiZ6Mt5wNumXwgkvPtIKbRFYHokm59Wo18j6NoI=; b=HK8kfcACtI+MUBGCb95vlfazjnMmXHuzR0lW6Z9GTitwbo5EBRuBR7sX5om2aKnn84 SgMdgjPl/SjBZRiwFzK9wdYhxHQUNNYNqyaRhGLaFinWU7pRM55B7YK0SVdbwrNDRGyy 16XjbBRpEvYPJH+SPRrepzo2lleXCpufMDkljO3GOUhSoudD7/jozbJSh+J17UINbJeJ 8TXfQopE59AY0BEUlG3h11rKl3AvqzCRQaANXbqaRSLhsSCAzkUTvuPFqCjUPzzQthNU i5NtT9PRci50i/sEFp881A1st/4+xVeYjJiYWPUiGGBHTTXrS+2njqYVP07s8thoypWk 9p5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/QSgLiZ6Mt5wNumXwgkvPtIKbRFYHokm59Wo18j6NoI=; b=eqQ7XW0tysp/2d7tD97CeCquAIoRBcb2QqarfTgtVJpHsdejZWWdzCI8JjkE2k9AtP zMY9n39VdUJKBqeCMB73btQ1BL3qmlEg4NA3Vw1JzoS70Ac3o8dHyR8imVZEKV6lcDS6 2RGY23c+2kg4NJ8eczva/V9LxdyJi8/iEHXTHZJuLFvIYeJFqON/p/2Azs/gIVLjPeXA N1HWqZFxpMHQiYAMMY4VQxblRiJJuGHALVlznAf9gATdOcww2lvuj3KJPI8aSNzZ/gS0 O9dfDjLaFVP+3E+DQos+ihq36ZhfsBaNPPU67EYso2f7eSoQcHTbhZm8BzJGSY0bvRUi es9g== X-Gm-Message-State: ABuFfojY92Qf3eVKyODt+Nz5KB4K7DGWTD1GwQsdxY+JG+ze78TRVth9 LUYya+ZCoR3W+nNglWMy2r9KbdvnWL4= X-Google-Smtp-Source: ACcGV61HENa34BLjaqbc1itviK1urK+fYaabECdIdfK1xId45YdIzrr1SZ6YP2wCJ5xQGp2D1xbXqw== X-Received: by 2002:a63:4658:: with SMTP id v24-v6mr1774331pgk.425.1538579368687; Wed, 03 Oct 2018 08:09:28 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:36 +0700 Message-Id: <1538579266-8389-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v1 02/12] net: cadence_gem: Announce availability of priority queues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Announce the availability of the various priority queues. This fixes an issue where guest kernels would miss to configure secondary queues due to inproper feature bits. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/net/cadence_gem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index e560b7a..901c173 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1213,6 +1213,7 @@ static void gem_reset(DeviceState *d) int i; CadenceGEMState *s =3D CADENCE_GEM(d); const uint8_t *a; + uint32_t queues_mask; =20 DB_PRINT("\n"); =20 @@ -1229,7 +1230,10 @@ static void gem_reset(DeviceState *d) s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; s->regs[GEM_DESCONF5] =3D 0x002f2045; - s->regs[GEM_DESCONF6] =3D 0x00000200; + s->regs[GEM_DESCONF6] =3D 0x0; + + queues_mask =3D MAKE_64BIT_MASK(1, s->num_priority_queues - 1); + s->regs[GEM_DESCONF6] |=3D queues_mask; =20 /* Set MAC address */ a =3D &s->conf.macaddr.a[0]; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579536252795.1167467319887; Wed, 3 Oct 2018 08:12:16 -0700 (PDT) Received: from localhost ([::1]:49232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7ioo-0007kO-KC for importer@patchew.org; Wed, 03 Oct 2018 11:12:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7imt-0005kF-EW for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:10:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7ims-0004bW-Ec for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:10:07 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:42704) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7imq-0004b3-EE; Wed, 03 Oct 2018 11:10:04 -0400 Received: by mail-pg1-x530.google.com with SMTP id i4-v6so1700367pgq.9; Wed, 03 Oct 2018 08:10:04 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id p13-v6sm6387049pfd.65.2018.10.03.08.10.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:10:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YDD93BkvlhktRMuNmt6kFqzFq9lqnMzaZQtTkxxOD/Y=; b=tTGLOiOG3+1QrERUQyxExkb02UPvnBTjdQBHtOE2YlyjvpQe/leijG592WK6RcaHGu 02BlECPnbNEfLXGQ+XYWZcwioz+SOhvZ+pcXjEZY2AqCx3iNs5NKDLR7DZbSF+JF7N3D 3xEbpKFx9kfBTcDgFZNZIsANvzZJb9YoYHfzjl31U/DRLJXFSM0vkiQetx+t6dEYIQ1Y zPQ/TssperZo0CMoBYFESFHg4CwPC1KjEZGe5w5Q09Uv8f/IECmo29YG+xXMHbgL2xo3 6dgLR5SJ6UiNWK7sVLwmC3HFC8M6Cv8lyp24zuK3G0Ji8bp5rArO0GpKzhB392eMpm0I paug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YDD93BkvlhktRMuNmt6kFqzFq9lqnMzaZQtTkxxOD/Y=; b=eFiyALyaaTRw2eKv/1UbKxf0H/DLQw+6/iFBCKJM3cnMzZCnuAA6d1egI86Lt52ezO YD2XDH/FTrDREebU4v1U85Pz85btSKZzb6n746/ic8uNaVdA2pX3DEUaUiCq7pxqjGN8 m4SJPa3MlsoLpR9ZUKQpqnXnMdGha1RDjSkguTeh/SCUlBaxMlr9i/T3YWrs3kEmUWOe q2lqNgJn07bARXNXRGlPk3E0BMho9EIfhjiJNrvkuCa6dSEV0n/Sw8yKNkwcKJOCi6LM IwqKvI7hQiembFnAgbsMrHkX5eG5vOpbk6+C2M8glzb60P+TKp1BO9wj6NL3vlQmSuuC gbWw== X-Gm-Message-State: ABuFfog1v71vGcGY0Uy01t4jof3MJjHKVgUBGHyR441DQtU3eLcho/rg CFWdJzehBKOX8KD38t8J170jP+do4sM= X-Google-Smtp-Source: ACcGV60SknFzw+NveJ8pqVaIj2snZbS28kDu1KX2Ad06r0LMvOAqMtrCISWW3rnxYbcveyz3CGwQzA== X-Received: by 2002:a63:a362:: with SMTP id v34-v6mr1796402pgn.261.1538579402985; Wed, 03 Oct 2018 08:10:02 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:37 +0700 Message-Id: <1538579266-8389-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH v1 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Use uint32_t instead of unsigned to describe 32bit descriptor words. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/cadence_gem.c | 42 +++++++++++++++++++++-------------------= -- include/hw/net/cadence_gem.h | 2 +- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 901c173..31f3fe0 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -302,42 +302,42 @@ =20 #define GEM_MODID_VALUE 0x00020118 =20 -static inline unsigned tx_desc_get_buffer(unsigned *desc) +static inline unsigned tx_desc_get_buffer(uint32_t *desc) { return desc[0]; } =20 -static inline unsigned tx_desc_get_used(unsigned *desc) +static inline unsigned tx_desc_get_used(uint32_t *desc) { return (desc[1] & DESC_1_USED) ? 1 : 0; } =20 -static inline void tx_desc_set_used(unsigned *desc) +static inline void tx_desc_set_used(uint32_t *desc) { desc[1] |=3D DESC_1_USED; } =20 -static inline unsigned tx_desc_get_wrap(unsigned *desc) +static inline unsigned tx_desc_get_wrap(uint32_t *desc) { return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; } =20 -static inline unsigned tx_desc_get_last(unsigned *desc) +static inline unsigned tx_desc_get_last(uint32_t *desc) { return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; } =20 -static inline void tx_desc_set_last(unsigned *desc) +static inline void tx_desc_set_last(uint32_t *desc) { desc[1] |=3D DESC_1_TX_LAST; } =20 -static inline unsigned tx_desc_get_length(unsigned *desc) +static inline unsigned tx_desc_get_length(uint32_t *desc) { return desc[1] & DESC_1_LENGTH; } =20 -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) { DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); DB_PRINT("bufaddr: 0x%08x\n", *desc); @@ -347,58 +347,58 @@ static inline void print_gem_tx_desc(unsigned *desc, = uint8_t queue) DB_PRINT("length: %d\n", tx_desc_get_length(desc)); } =20 -static inline unsigned rx_desc_get_buffer(unsigned *desc) +static inline unsigned rx_desc_get_buffer(uint32_t *desc) { return desc[0] & ~0x3UL; } =20 -static inline unsigned rx_desc_get_wrap(unsigned *desc) +static inline unsigned rx_desc_get_wrap(uint32_t *desc) { return desc[0] & DESC_0_RX_WRAP ? 1 : 0; } =20 -static inline unsigned rx_desc_get_ownership(unsigned *desc) +static inline unsigned rx_desc_get_ownership(uint32_t *desc) { return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; } =20 -static inline void rx_desc_set_ownership(unsigned *desc) +static inline void rx_desc_set_ownership(uint32_t *desc) { desc[0] |=3D DESC_0_RX_OWNERSHIP; } =20 -static inline void rx_desc_set_sof(unsigned *desc) +static inline void rx_desc_set_sof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_SOF; } =20 -static inline void rx_desc_set_eof(unsigned *desc) +static inline void rx_desc_set_eof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_EOF; } =20 -static inline void rx_desc_set_length(unsigned *desc, unsigned len) +static inline void rx_desc_set_length(uint32_t *desc, unsigned len) { desc[1] &=3D ~DESC_1_LENGTH; desc[1] |=3D len; } =20 -static inline void rx_desc_set_broadcast(unsigned *desc) +static inline void rx_desc_set_broadcast(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_BROADCAST; } =20 -static inline void rx_desc_set_unicast_hash(unsigned *desc) +static inline void rx_desc_set_unicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_UNICAST_HASH; } =20 -static inline void rx_desc_set_multicast_hash(unsigned *desc) +static inline void rx_desc_set_multicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_MULTICAST_HASH; } =20 -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) { desc[1] =3D deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_= LENGTH, sar_idx); @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState = *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - unsigned desc[2]; + uint32_t desc[2]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) =20 /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - unsigned desc_first[2]; + uint32_t desc_first[2]; =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 35de622..633d564 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -74,7 +74,7 @@ typedef struct CadenceGEMState { =20 uint8_t can_rx_state; /* Debug only */ =20 - unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; =20 bool sar_active[4]; } CadenceGEMState; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579669837479.5271487817997; Wed, 3 Oct 2018 08:14:29 -0700 (PDT) Received: from localhost ([::1]:49253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7ir6-0002aO-Mo for importer@patchew.org; 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Wed, 03 Oct 2018 08:10:36 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:38 +0700 Message-Id: <1538579266-8389-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v1 04/12] net: cadence_gem: Add macro with max number of descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add macro with max number of DMA descriptor words. No functional change. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/cadence_gem.c | 4 ++-- include/hw/net/cadence_gem.h | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 31f3fe0..4d769b0 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState = *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - uint32_t desc[2]; + uint32_t desc[DESC_MAX_NUM_WORDS]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) =20 /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - uint32_t desc_first[2]; + uint32_t desc_first[DESC_MAX_NUM_WORDS]; =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 633d564..b33ef65 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -32,6 +32,9 @@ =20 #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM addre= ss */ =20 +/* Max number of words in a DMA descriptor. */ +#define DESC_MAX_NUM_WORDS 2 + #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 #define MAX_TYPE2_SCREENERS 16 @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { =20 uint8_t can_rx_state; /* Debug only */ =20 - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; =20 bool sar_active[4]; } CadenceGEMState; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579857992433.2436565684078; Wed, 3 Oct 2018 08:17:37 -0700 (PDT) Received: from localhost ([::1]:49277 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7iu4-0004sd-Ky for importer@patchew.org; Wed, 03 Oct 2018 11:17:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7io5-0007az-4Z for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:11:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7io1-00051A-DK for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:11:21 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:39781) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7inz-0004zi-Fo; Wed, 03 Oct 2018 11:11:16 -0400 Received: by mail-pg1-x52d.google.com with SMTP id r9-v6so1711946pgv.6; Wed, 03 Oct 2018 08:11:11 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id n13-v6sm1922319pgr.73.2018.10.03.08.11.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eIg7KNhUJ/2g8KgJ36U2q28z1ATwXQD6Tl26WArvSYk=; b=cv37pPekFxfP6WEwSauIucI2sbsKmiFEtM9N00MDjzf2G6KkF0BbvFKhxtneHkYVN2 HUVDOnXD9Vm1j8BxOuQdggMyd4dGREa56kmOy0WILHbL7Mdlds84fcsy17hW/Wh7lmn+ vnmUFBBhQzoVuqD/j/p10mdq4sRChn88Zzc0+Z+XP10FxNOvQXP/czPJ9pNtKiORhZO4 0ugoBeUgdTjBmxgOfiKVWJ5XREWn53FFUQaotbR9lW6sLrN6bRgNab4S68/MAGpzrHci YhqRyAdhfw4O+w1lnjw7Nh6Tt/0cXeCYNPy07tY3LHLjNVBqcwIHvIoiIfAXKNO6Dg2e RQ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eIg7KNhUJ/2g8KgJ36U2q28z1ATwXQD6Tl26WArvSYk=; b=MLr2esg8w5T4lBPhOOJAfZDkBHOl+aPJAwDj4aNaljCB6EyopKZC7Hv2wO+7oP+2/4 93vxq3w5lCafR9AF5rs82d5Q7QtXRg8lblq22kv9ictFpIPOJvk006AKPr8lv2vErTLi Jo2ef6DJDA9mVVFsU5u3MyY7zmVWuICdlR1ZzZ/V4pnTVNjf7Ljm4GyJC/siYcydOi0Y lLREwjnngszh8Vr3M8rkQ8uGPT9X0QHe+Qq/cfVkT1RdqymaMDDXAZ/LXsH0UfAwSUr4 5PaO8icFCuXPacd++y/VIZaL/PUJFixvnlgtiW3VrL19WKVXp9Rz4XZ5V97d0rqLkueX 5GuQ== X-Gm-Message-State: ABuFfog/OmInlLl/Bu5Td8k7Jgos56GdVH0K7OmR8w38ZZ5nfrd5v4BJ 6rqpJIRu0iofxZ5wI2UNULZxSZr/UxE= X-Google-Smtp-Source: ACcGV62f6kTp11yaFSFFigWV1QMPxcu7tYJ3lOmfBl4l+v3uqOJFqFaXHdUEAgAs9ShW9XJB1bbaqA== X-Received: by 2002:a63:ea0e:: with SMTP id c14-v6mr1668856pgi.361.1538579470534; Wed, 03 Oct 2018 08:11:10 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:39 +0700 Message-Id: <1538579266-8389-6-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH v1 05/12] net: cadence_gem: Add support for extended descriptors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add support for extended descriptors with optional 64bit addressing and timestamping. QEMU will not yet provide timestamps (always leaving the valid timestamp bit as zero). Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/net/cadence_gem.c | 69 ++++++++++++++++++++++++++++++++--------= ---- include/hw/net/cadence_gem.h | 2 +- 2 files changed, 52 insertions(+), 19 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 4d769b0..759c1d7 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -207,6 +207,9 @@ #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ =20 +#define GEM_DMACFG_ADDR_64B (1U << 30) +#define GEM_DMACFG_TX_BD_EXT (1U << 29) +#define GEM_DMACFG_RX_BD_EXT (1U << 28) #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier= */ @@ -302,9 +305,14 @@ =20 #define GEM_MODID_VALUE 0x00020118 =20 -static inline unsigned tx_desc_get_buffer(uint32_t *desc) +static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *de= sc) { - return desc[0]; + uint64_t ret =3D desc[0]; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret |=3D (uint64_t)desc[2] << 32; + } + return ret; } =20 static inline unsigned tx_desc_get_used(uint32_t *desc) @@ -347,9 +355,30 @@ static inline void print_gem_tx_desc(uint32_t *desc, u= int8_t queue) DB_PRINT("length: %d\n", tx_desc_get_length(desc)); } =20 -static inline unsigned rx_desc_get_buffer(uint32_t *desc) +static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *de= sc) { - return desc[0] & ~0x3UL; + uint64_t ret =3D desc[0] & ~0x3UL; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret |=3D (uint64_t)desc[2] << 32; + } + return ret; +} + +static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) +{ + int ret =3D 2; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret +=3D 2; + } + if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT + : GEM_DMACFG_TX_BD_EXT)) { + ret +=3D 2; + } + + assert(ret <=3D DESC_MAX_NUM_WORDS); + return ret; } =20 static inline unsigned rx_desc_get_wrap(uint32_t *desc) @@ -419,7 +448,7 @@ static void gem_init_register_masks(CadenceGEMState *s) memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); s->regs_ro[GEM_NWCTRL] =3D 0xFFF80000; s->regs_ro[GEM_NWSTATUS] =3D 0xFFFFFFFF; - s->regs_ro[GEM_DMACFG] =3D 0xFE00F000; + s->regs_ro[GEM_DMACFG] =3D 0x8E00F000; s->regs_ro[GEM_TXSTATUS] =3D 0xFFFFFE08; s->regs_ro[GEM_RXQBASE] =3D 0x00000003; s->regs_ro[GEM_TXQBASE] =3D 0x00000003; @@ -807,7 +836,8 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); /* read current descriptor */ cpu_physical_memory_read(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q= ])); + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { @@ -926,9 +956,10 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) rx_desc_get_buffer(s->rx_desc[q])); =20 /* Copy packet data to emulated DMA buffer */ - cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + - rxbuf_off= set, - rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)= ); + cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + + rxbuf_of= fset, + rxbuf_ptr, + MIN(bytes_to_copy, rxbufsize)); rxbuf_ptr +=3D MIN(bytes_to_copy, rxbufsize); bytes_to_copy -=3D MIN(bytes_to_copy, rxbufsize); =20 @@ -964,7 +995,7 @@ static ssize_t gem_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) /* Descriptor write-back. */ cpu_physical_memory_write(s->rx_desc_addr[q], (uint8_t *)s->rx_desc[q], - sizeof(s->rx_desc[q])); + sizeof(uint32_t) * gem_get_desc_len(s, t= rue)); =20 /* Next descriptor */ if (rx_desc_get_wrap(s->rx_desc[q])) { @@ -972,7 +1003,7 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) s->rx_desc_addr[q] =3D s->regs[GEM_RXQBASE]; } else { DB_PRINT("incrementing RX descriptor list\n"); - s->rx_desc_addr[q] +=3D 8; + s->rx_desc_addr[q] +=3D 4 * gem_get_desc_len(s, true); } =20 gem_get_rx_desc(s, q); @@ -1069,7 +1100,8 @@ static void gem_transmit(CadenceGEMState *s) =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, sizeof(desc)); + (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, fa= lse)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) =3D=3D 0) { =20 @@ -1082,7 +1114,7 @@ static void gem_transmit(CadenceGEMState *s) /* The real hardware would eat this (and possibly crash). * For QEMU let's lend a helping hand. */ - if ((tx_desc_get_buffer(desc) =3D=3D 0) || + if ((tx_desc_get_buffer(s, desc) =3D=3D 0) || (tx_desc_get_length(desc) =3D=3D 0)) { DB_PRINT("Invalid TX descriptor @ 0x%x\n", (unsigned)packet_desc_addr); @@ -1101,7 +1133,7 @@ static void gem_transmit(CadenceGEMState *s) /* Gather this fragment of the packet from "dma memory" to our * contig buffer. */ - cpu_physical_memory_read(tx_desc_get_buffer(desc), p, + cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, tx_desc_get_length(desc)); p +=3D tx_desc_get_length(desc); total_bytes +=3D tx_desc_get_length(desc); @@ -1124,7 +1156,8 @@ static void gem_transmit(CadenceGEMState *s) if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] =3D s->regs[GEM_TXQBASE]; } else { - s->tx_desc_addr[q] =3D packet_desc_addr + 8; + s->tx_desc_addr[q] =3D packet_desc_addr + + 4 * gem_get_desc_len(s, false); } DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q= ]); =20 @@ -1168,11 +1201,11 @@ static void gem_transmit(CadenceGEMState *s) tx_desc_set_last(desc); packet_desc_addr =3D s->regs[GEM_TXQBASE]; } else { - packet_desc_addr +=3D 8; + packet_desc_addr +=3D 4 * gem_get_desc_len(s, false); } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_a= ddr); - cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, sizeof(desc)); + cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, fal= se)); } =20 if (tx_desc_get_used(desc)) { diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index b33ef65..00dbf4f 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -33,7 +33,7 @@ #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM addre= ss */ =20 /* Max number of words in a DMA descriptor. */ -#define DESC_MAX_NUM_WORDS 2 +#define DESC_MAX_NUM_WORDS 6 =20 #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v1 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add support for selecting the Memory Region that the GEM will do DMA to. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/cadence_gem.c | 63 ++++++++++++++++++++++++++++------------= ---- include/hw/net/cadence_gem.h | 2 ++ 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 759c1d7..ab02515 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -28,6 +28,7 @@ #include "hw/net/cadence_gem.h" #include "qapi/error.h" #include "qemu/log.h" +#include "sysemu/dma.h" #include "net/checksum.h" =20 #ifdef CADENCE_GEM_ERR_DEBUG @@ -835,9 +836,9 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) { DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); /* read current descriptor */ - cpu_physical_memory_read(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], - sizeof(uint32_t) * gem_get_desc_len(s, true)); + address_space_read(s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFI= ED, + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { @@ -956,10 +957,10 @@ static ssize_t gem_receive(NetClientState *nc, const = uint8_t *buf, size_t size) rx_desc_get_buffer(s->rx_desc[q])); =20 /* Copy packet data to emulated DMA buffer */ - cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + + address_space_write(s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]= ) + rxbuf_of= fset, - rxbuf_ptr, - MIN(bytes_to_copy, rxbufsize)); + MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, + MIN(bytes_to_copy, rxbufsize)); rxbuf_ptr +=3D MIN(bytes_to_copy, rxbufsize); bytes_to_copy -=3D MIN(bytes_to_copy, rxbufsize); =20 @@ -993,9 +994,10 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) } =20 /* Descriptor write-back. */ - cpu_physical_memory_write(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], - sizeof(uint32_t) * gem_get_desc_len(s, t= rue)); + address_space_write(s->dma_as, s->rx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Next descriptor */ if (rx_desc_get_wrap(s->rx_desc[q])) { @@ -1099,9 +1101,9 @@ static void gem_transmit(CadenceGEMState *s) packet_desc_addr =3D s->tx_desc_addr[q]; =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); - cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, fa= lse)); + address_space_read(s->dma_as, packet_desc_addr, + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, false)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) =3D=3D 0) { =20 @@ -1133,8 +1135,9 @@ static void gem_transmit(CadenceGEMState *s) /* Gather this fragment of the packet from "dma memory" to our * contig buffer. */ - cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, - tx_desc_get_length(desc)); + address_space_read(s->dma_as, tx_desc_get_buffer(s, desc), + MEMTXATTRS_UNSPECIFIED, + p, tx_desc_get_length(desc)); p +=3D tx_desc_get_length(desc); total_bytes +=3D tx_desc_get_length(desc); =20 @@ -1145,13 +1148,15 @@ static void gem_transmit(CadenceGEMState *s) /* Modify the 1st descriptor of this packet to be owned by * the processor. */ - cpu_physical_memory_read(s->tx_desc_addr[q], - (uint8_t *)desc_first, - sizeof(desc_first)); + address_space_read(s->dma_as, s->tx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)desc_first, + sizeof(desc_first)); tx_desc_set_used(desc_first); - cpu_physical_memory_write(s->tx_desc_addr[q], - (uint8_t *)desc_first, - sizeof(desc_first)); + address_space_write(s->dma_as, s->tx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)desc_first, + sizeof(desc_first)); /* Advance the hardware current descriptor past this packe= t */ if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] =3D s->regs[GEM_TXQBASE]; @@ -1204,8 +1209,9 @@ static void gem_transmit(CadenceGEMState *s) packet_desc_addr +=3D 4 * gem_get_desc_len(s, false); } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_a= ddr); - cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, fal= se)); + address_space_read(s->dma_as, packet_desc_addr, + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, false= )); } =20 if (tx_desc_get_used(desc)) { @@ -1500,6 +1506,13 @@ static void gem_realize(DeviceState *dev, Error **er= rp) CadenceGEMState *s =3D CADENCE_GEM(dev); int i; =20 + if (s->dma_mr) { + s->dma_as =3D g_malloc0(sizeof(AddressSpace)); + address_space_init(s->dma_as, s->dma_mr, NULL); + } else { + s->dma_as =3D &address_space_memory; + } + if (s->num_priority_queues =3D=3D 0 || s->num_priority_queues > MAX_PRIORITY_QUEUES) { error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, @@ -1537,6 +1550,12 @@ static void gem_init(Object *obj) "enet", sizeof(s->regs)); =20 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); } =20 static const VMStateDescription vmstate_cadence_gem =3D { diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 00dbf4f..c8f0751 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -45,6 +45,8 @@ typedef struct CadenceGEMState { =20 /*< public >*/ MemoryRegion iomem; + MemoryRegion *dma_mr; + AddressSpace *dma_as; NICState *nic; NICConf conf; qemu_irq irq[MAX_PRIORITY_QUEUES]; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538580197809186.68856807091083; Wed, 3 Oct 2018 08:23:17 -0700 (PDT) Received: from localhost ([::1]:49315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7izc-00028K-98 for importer@patchew.org; Wed, 03 Oct 2018 11:23:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7ip5-0000CG-UF for qemu-devel@nongnu.org; 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Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:41 +0700 Message-Id: <1538579266-8389-8-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v1 07/12] net: cadence_gem: Implement support for 64bit descriptor addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Implement support for 64bit descriptor addresses. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/net/cadence_gem.c | 47 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index ab02515..f93cd8e 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -153,6 +153,9 @@ #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) =20 +#define GEM_TBQPH (0x000004C8 / 4) +#define GEM_RBQPH (0x000004D4 / 4) + #define GEM_INT_Q1_ENABLE (0x00000600 / 4) #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) =20 @@ -832,18 +835,42 @@ static int get_queue_from_screen(CadenceGEMState *s, = uint8_t *rxbuf_ptr, return 0; } =20 +static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) +{ + hwaddr desc_addr =3D 0; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + desc_addr =3D s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; + } + desc_addr <<=3D 32; + desc_addr |=3D tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; + return desc_addr; +} + +static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) +{ + return gem_get_desc_addr(s, true, q); +} + +static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) +{ + return gem_get_desc_addr(s, false, q); +} + static void gem_get_rx_desc(CadenceGEMState *s, int q) { - DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); + hwaddr desc_addr =3D gem_get_rx_desc_addr(s, q); + + DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); + /* read current descriptor */ - address_space_read(s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFI= ED, + address_space_read(s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { - DB_PRINT("descriptor 0x%x owned by sw.\n", - (unsigned)s->rx_desc_addr[q]); + DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr= ); s->regs[GEM_RXSTATUS] |=3D GEM_RXSTATUS_NOBUF; s->regs[GEM_ISR] |=3D GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); /* Handle interrupt consequences */ @@ -947,6 +974,8 @@ static ssize_t gem_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) q =3D get_queue_from_screen(s, rxbuf_ptr, rxbufsize); =20 while (bytes_to_copy) { + hwaddr desc_addr; + /* Do nothing if receive is not enabled. */ if (!gem_can_receive(nc)) { assert(!first_desc); @@ -994,7 +1023,8 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) } =20 /* Descriptor write-back. */ - address_space_write(s->dma_as, s->rx_desc_addr[q], + desc_addr =3D gem_get_rx_desc_addr(s, q); + address_space_write(s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); @@ -1098,7 +1128,7 @@ static void gem_transmit(CadenceGEMState *s) =20 for (q =3D s->num_priority_queues - 1; q >=3D 0; q--) { /* read current descriptor */ - packet_desc_addr =3D s->tx_desc_addr[q]; + packet_desc_addr =3D gem_get_tx_desc_addr(s, q); =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(s->dma_as, packet_desc_addr, @@ -1144,16 +1174,17 @@ static void gem_transmit(CadenceGEMState *s) /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { uint32_t desc_first[DESC_MAX_NUM_WORDS]; + hwaddr desc_addr =3D gem_get_tx_desc_addr(s, q); =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. */ - address_space_read(s->dma_as, s->tx_desc_addr[q], + address_space_read(s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc_first, sizeof(desc_first)); tx_desc_set_used(desc_first); - address_space_write(s->dma_as, s->tx_desc_addr[q], + address_space_write(s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc_first, sizeof(desc_first)); --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:42 +0700 Message-Id: <1538579266-8389-9-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v1 08/12] net: cadence_gem: Announce 64bit addressing support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Announce 64bit addressing support. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/net/cadence_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index f93cd8e..fc81fb5 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -142,6 +142,7 @@ #define GEM_DESCONF4 (0x0000028C/4) #define GEM_DESCONF5 (0x00000290/4) #define GEM_DESCONF6 (0x00000294/4) +#define GEM_DESCONF6_64B_MASK (1U << 23) #define GEM_DESCONF7 (0x00000298/4) =20 #define GEM_INT_Q1_STATUS (0x00000400 / 4) @@ -1300,7 +1301,7 @@ static void gem_reset(DeviceState *d) s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; s->regs[GEM_DESCONF5] =3D 0x002f2045; - s->regs[GEM_DESCONF6] =3D 0x0; + s->regs[GEM_DESCONF6] =3D GEM_DESCONF6_64B_MASK; =20 queues_mask =3D MAKE_64BIT_MASK(1, s->num_priority_queues - 1); s->regs[GEM_DESCONF6] |=3D queues_mask; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538579754593561.2586180709634; Wed, 3 Oct 2018 08:15:54 -0700 (PDT) Received: from localhost ([::1]:49266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7isP-0003id-Ac for importer@patchew.org; Wed, 03 Oct 2018 11:15:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7iqC-0002A4-29 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:13:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7iq9-0006UC-4V for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:13:32 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:46148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7iq8-0006TT-U2; Wed, 03 Oct 2018 11:13:29 -0400 Received: by mail-pg1-x544.google.com with SMTP id a5-v6so1693023pgv.13; Wed, 03 Oct 2018 08:13:28 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id t26-v6sm3140106pfa.158.2018.10.03.08.13.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:13:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9Ay3M6y+W3ArY+Q25A5a/bdjSssGSlE2NegpVjfAXco=; b=ZhV3lT0DoIRREMxrlgiqx+ThzbpVhLiiP5xO5V5lPhgYIADZ2hrOu9dsCUWf2yEIqY /nEIcomqj3Ft1X2k5S3OGXb7VPSPIFGuAy4oW2JiHhHzxVspK93xDOCe5J9TApEYd20i vv67Jvpytvz7MDKT5Ai3aKI8oEgeFg98XdCkwn4yoKFQBuX9rZOk6TaPYFz21SRXTCX8 /znzlFDfobqpmBkQpBtKC04duyXwG7H4kPxkjYKsYQAhAzKjWhk6+GiibKfSJ/9tbIpm QVJNyZCkdjUMowgMd3i6nXf2NARJ91i+5MoBQ2WMSdGHuGTg2NuTNNZKiD8WkmEaVnkj 8hHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9Ay3M6y+W3ArY+Q25A5a/bdjSssGSlE2NegpVjfAXco=; b=W9XTocd39ctlnrsNwThAuZ/lXEzRggQSdqTCuJp8MtWwB2ciiKfzaD2eHtkdqRQBQr eZVahGFNeceqD5Z1VcIq+DR1mBKGLk0eYo4OOW0oczVR3k0oZblxO2x9bjME5ctw2pzN V+3FpAjWVcmm4SdVtkB8jZ6kIZUdFKN+vpfU6BWIQerUKmXrM7DRkYx+gSWL7JiwH89m /Y0Y32E4YRMER+XnCIhfuGVeTP3BgQAN9MM5YQ10L0gbB3BUwDlq9kgEJ75gsgOuEg0E i6NiNiqVw7P1vEGSBSTYZKS2/plvVQotc5gI1tJo6DyDPooV1e1GcMC5YylIHDTdvItw h9oQ== X-Gm-Message-State: ABuFfogLjhyZlrVNYsFrqo7YW0rLtIxz3dQxcvaZ8xRh95VGdpBU8l2q Lrn2To1dtEB+s/RpkB5RWYZetm+gZLA= X-Google-Smtp-Source: ACcGV63PdAQZkJ4dIPXcS7cj0wTAz3eufoUzlrTIEIvrYHUVB8vqOM8uhXdFFqOtzL2LiUi0U6H3Tw== X-Received: by 2002:a63:7f0e:: with SMTP id a14-v6mr1788747pgd.296.1538579606798; Wed, 03 Oct 2018 08:13:26 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:43 +0700 Message-Id: <1538579266-8389-10-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v1 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" When QEMU provides the equivalent of the EL3 firmware, we need to enable HVCs in scr_el3 when turning on CPUs that target EL2. Signed-off-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- target/arm/arm-powerctl.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb..54f2974 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cp= u_state, struct CpuOnInfo *info =3D (struct CpuOnInfo *) data.host_ptr; =20 /* Initialize the cpu we are turning on */ + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); cpu_reset(target_cpu_state); target_cpu_state->halted =3D 0; =20 @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |=3D SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we ne= ed + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el =3D=3D 2) { + target_cpu->env.cp15.scr_el3 |=3D SCR_HCE; + } } =20 /* We check if the started CPU is now at the correct level */ --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538580369236569.072695895223; Wed, 3 Oct 2018 08:26:09 -0700 (PDT) Received: from localhost ([::1]:49334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7j2J-0004HN-Op for importer@patchew.org; Wed, 03 Oct 2018 11:26:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49022) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7iql-0002et-0H for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:14:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7iqh-0006fr-FF for qemu-devel@nongnu.org; Wed, 03 Oct 2018 11:14:06 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:37198) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7iqh-0006fK-5W; Wed, 03 Oct 2018 11:14:03 -0400 Received: by mail-pl1-x642.google.com with SMTP id az3-v6so3635397plb.4; Wed, 03 Oct 2018 08:14:01 -0700 (PDT) Received: from localhost ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id e19-v6sm3562371pfb.153.2018.10.03.08.13.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 08:13:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TjadI8cUCVkRuIbycVSHfp34CxaXn6Lxf6cziK2DDYk=; b=XNDt9qRPitTOoTezy3vBJaAE1E/2fGkz3LWDn69uAc9ikLCfAmpuT9niMtfqWXklXA u2L1jvvpPQgly6CfsvbsiWFjRJ2LNIcaFy57cV52RSPtd+2nvuc+pQ1hK5ivFWbtjPi0 uoOLpR6bAkwx1wjQU16sYzHdoMTxQohJJpCeoIv336+EHR1osD+M7gvo//VlM5qGmX5z XFXzC9PzyncOLsoipmGa6c8ucMochTINkU6x19CkpWHN0k946O1XpnAOu0ff0fnWRRCx 9CGp+CWvWqq9Z50PEviR6M6WiqoWeFVGV9DK0ewz1buyimkn3QNnWHl9BcWFZ7CZ0LD9 xvAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TjadI8cUCVkRuIbycVSHfp34CxaXn6Lxf6cziK2DDYk=; b=IxT82rFDzLhFrwGvo+93bc6txjf8AIOEoHgTZO50t5ZydIpBK9wA1bpCrtEdHw9MfA nsMiIKr+RX77BDLTtAhINgELz8JKVwD9uVPa+OYutih35vrJCjRPL6xBTl2BqC9dwEPP rUjtnH7zEwB575fyhx4um5/fwZVJsYkUtIUflfJYNKgBJY3pCxEScvORTcbdnv8Uoh2P gmTBE1E0cwU3GmINdNHaFJXMrEuJDxMeEXQ5PVKWdR7nkCOk9n3InTUHGHYYEtf14ghI Djf2mk/3WrxA+JB+rlXpD3W7YaVxdaYFWlu8cP94T71ametfF1C27HziBMi92riq6b0R DoJg== X-Gm-Message-State: ABuFfoj2OZ1z5z1o8yqPpMN9IFpiGG/teGlkjpyFNKedm+AaoqW33NEp oy0mxW4BnjeUnUHVu/rkxvfRWXjg6rA= X-Google-Smtp-Source: ACcGV62ncrtswY9tTl/+5IhsWqcgjvEFK9SzLx92jjGzf4Jh7BBjU7UQKYF6J7phpuLm6hPFvJ/e+A== X-Received: by 2002:a17:902:43e4:: with SMTP id j91-v6mr2162438pld.74.1538579640593; Wed, 03 Oct 2018 08:14:00 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:44 +0700 Message-Id: <1538579266-8389-11-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v1 10/12] target/arm: Add the Cortex-A72 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add the ARM Cortex-A72. Signed-off-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 800bff7..02e500b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -218,6 +218,64 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } =20 +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fd083; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034080; + cpu->mvfr0 =3D 0x10110222; + cpu->mvfr1 =3D 0x12111111; + cpu->mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->id_pfr0 =3D 0x00000131; + cpu->id_pfr1 =3D 0x00011011; + cpu->id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x10201105; + cpu->id_mmfr1 =3D 0x40000000; + cpu->id_mmfr2 =3D 0x01260000; + cpu->id_mmfr3 =3D 0x02102211; + cpu->id_isar0 =3D 0x02101110; + cpu->id_isar1 =3D 0x13112111; + cpu->id_isar2 =3D 0x21232042; + cpu->id_isar3 =3D 0x01112131; + cpu->id_isar4 =3D 0x00011142; + cpu->id_isar5 =3D 0x00011121; + cpu->id_aa64pfr0 =3D 0x00002222; + cpu->id_aa64dfr0 =3D 0x10305106; + cpu->pmceid0 =3D 0x00000000; + cpu->pmceid1 =3D 0x00000000; + cpu->id_aa64isar0 =3D 0x00011120; + cpu->id_aa64mmfr0 =3D 0x00001124; + cpu->dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -293,6 +351,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, + { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, { .name =3D NULL } }; --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v1 11/12] hw/arm: versal: Add a model of Xilinx Versal SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias --- default-configs/aarch64-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/xlnx-versal.c | 339 ++++++++++++++++++++++++++++++++= ++++ include/hw/arm/xlnx-versal.h | 122 +++++++++++++ 4 files changed, 463 insertions(+) create mode 100644 hw/arm/xlnx-versal.c create mode 100644 include/hw/arm/xlnx-versal.h diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-= softmmu.mak index 6f790f0..4ea9add 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -8,4 +8,5 @@ CONFIG_DDC=3Dy CONFIG_DPCD=3Dy CONFIG_XLNX_ZYNQMP=3Dy CONFIG_XLNX_ZYNQMP_ARM=3Dy +CONFIG_XLNX_VERSAL=3Dy CONFIG_ARM_SMMUV3=3Dy diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 5f88062..ec21d9b 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -26,6 +26,7 @@ obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboa= rd.o obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o +obj-$(CONFIG_XLNX_VERSAL) +=3D xlnx-versal.o obj-$(CONFIG_FSL_IMX25) +=3D fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c new file mode 100644 index 0000000..c12fc85 --- /dev/null +++ b/hw/arm/xlnx-versal.c @@ -0,0 +1,339 @@ +/* + * Xilinx Versal SoC model. + * + * Copyright (c) 2018 Xilinx Inc. + * Written by Edgar E. Iglesias + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "hw/sysbus.h" +#include "net/net.h" +#include "sysemu/sysemu.h" +#include "sysemu/kvm.h" +#include "hw/arm/arm.h" +#include "kvm_arm.h" +#include "hw/misc/unimp.h" +#include "hw/intc/arm_gicv3_common.h" +#include "hw/arm/xlnx-versal.h" + +#define XLNX_VERSAL_ACPU_TYPE "cortex-a72" "-" TYPE_ARM_CPU +#define GEM_REVISION 0x40070106 + +static void versal_create_apu_cpus(Versal *s, Error **errp) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { + Object *obj; + char *name; + + obj =3D object_new(XLNX_VERSAL_ACPU_TYPE); + if (!obj) { + /* Secondary CPUs start in PSCI powered-down state */ + error_setg(errp, "Unable to create apu.cpu[%d] of type %s", + i, XLNX_VERSAL_ACPU_TYPE); + return; + } + + name =3D g_strdup_printf("apu-cpu[%d]", i); + object_property_add_child(OBJECT(s), name, obj, &error_fatal); + g_free(name); + + object_property_set_int(obj, s->cfg.psci_conduit, + "psci-conduit", &error_abort); + if (i) { + object_property_set_bool(obj, true, + "start-powered-off", &error_abort); + } + + object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu), + "core-count", &error_abort); + object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory", + &error_abort); + object_property_set_bool(obj, true, "realized", &error_fatal); + s->fpd.apu.cpu[i] =3D ARM_CPU(obj); + } +} + +static void versal_create_apu_gic(Versal *s, qemu_irq *pic, Error **errp) +{ + static const uint64_t addrs[] =3D { + MM_GIC_APU_DIST_MAIN, + MM_GIC_APU_REDIST_0 + }; + SysBusDevice *gicbusdev; + DeviceState *gicdev; + int nr_apu_cpus =3D ARRAY_SIZE(s->fpd.apu.cpu); + int i; + + sysbus_init_child_obj(OBJECT(s), "apu-gic", + &s->fpd.apu.gic, sizeof(s->fpd.apu.gic), + gicv3_class_name()); + gicbusdev =3D SYS_BUS_DEVICE(&s->fpd.apu.gic); + gicdev =3D DEVICE(&s->fpd.apu.gic); + qdev_prop_set_uint32(gicdev, "revision", 3); + qdev_prop_set_uint32(gicdev, "num-cpu", 2); + qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); + qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); + qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2); + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(gicdev, "has-security-extensions", true); + } + + object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized", er= rp); + + for (i =3D 0; i < ARRAY_SIZE(addrs); i++) { + MemoryRegion *mr; + + mr =3D sysbus_mmio_get_region(gicbusdev, i); + memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); + } + + for (i =3D 0; i < nr_apu_cpus; i++) { + DeviceState *cpudev =3D DEVICE(s->fpd.apu.cpu[i]); + int ppibase =3D XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SG= IS; + qemu_irq maint_irq; + int ti; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D VERSAL_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D VERSAL_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D VERSAL_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D VERSAL_TIMER_S_EL1_IRQ, + }; + + for (ti =3D 0; ti < ARRAY_SIZE(timer_irq); ti++) { + qdev_connect_gpio_out(cpudev, ti, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[ti]= )); + } + maint_irq =3D qdev_get_gpio_in(gicdev, + ppibase + VERSAL_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", + 0, maint_irq); + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); + sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } + + for (i =3D 0; i < XLNX_VERSAL_NR_IRQS; i++) { + pic[i] =3D qdev_get_gpio_in(gicdev, i); + } +} + +static void versal_create_uarts(Versal *s, qemu_irq *pic) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { + static const int irqs[] =3D { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ= _0}; + static const uint64_t addrs[] =3D { MM_UART0, MM_UART1 }; + char *name =3D g_strdup_printf("uart%d", i); + DeviceState *dev; + MemoryRegion *mr; + + dev =3D qdev_create(NULL, "pl011"); + s->lpd.iou.uart[i] =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fat= al); + qdev_init_nofail(dev); + + mr =3D sysbus_mmio_get_region(s->lpd.iou.uart[i], 0); + memory_region_add_subregion(&s->mr_ps, addrs[i], mr); + + sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]); + g_free(name); + } +} + +static void versal_create_gems(Versal *s, qemu_irq *pic) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { + static const int irqs[] =3D { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0= }; + static const uint64_t addrs[] =3D { MM_GEM0, MM_GEM1 }; + char *name =3D g_strdup_printf("gem%d", i); + NICInfo *nd =3D &nd_table[i]; + DeviceState *dev; + MemoryRegion *mr; + + dev =3D qdev_create(NULL, "cadence_gem"); + s->lpd.iou.gem[i] =3D SYS_BUS_DEVICE(dev); + object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fat= al); + if (nd->used) { + qemu_check_nic_model(nd, "cadence_gem"); + qdev_set_nic_properties(dev, nd); + } + object_property_set_int(OBJECT(s->lpd.iou.gem[i]), + 2, "num-priority-queues", + &error_abort); + object_property_set_link(OBJECT(s->lpd.iou.gem[i]), + OBJECT(&s->mr_ps), "dma", + &error_abort); + qdev_init_nofail(dev); + + mr =3D sysbus_mmio_get_region(s->lpd.iou.gem[i], 0); + memory_region_add_subregion(&s->mr_ps, addrs[i], mr); + + sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]); + g_free(name); + } +} + +/* This takes the board allocated linear DDR memory and creates aliases + * for each split DDR range/apperture on the Versal address map. + */ +static void versal_map_ddr(Versal *s) +{ + uint64_t size =3D memory_region_size(s->cfg.mr_ddr); + /* Describes the various split DDR access regions. */ + static const struct { + uint64_t base; + uint64_t size; + } addr_ranges[] =3D { + { MM_TOP_DDR, MM_TOP_DDR_SIZE }, + { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, + { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, + { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } + }; + uint64_t offset =3D 0; + int i; + + assert(ARRAY_SIZE(addr_ranges) =3D=3D ARRAY_SIZE(s->noc.mr_ddr_ranges)= ); + for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { + char *name; + uint64_t mapsize; + + mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; + name =3D g_strdup_printf("noc-ddr-range%d", i); + /* Create the MR alias. */ + memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), + name, s->cfg.mr_ddr, + offset, mapsize); + + /* Map it onto the NoC MR. */ + memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, + &s->noc.mr_ddr_ranges[i]); + offset +=3D mapsize; + size -=3D mapsize; + g_free(name); + } +} + +static void versal_unimp_area(Versal *s, const char *name, + MemoryRegion *mr, + hwaddr base, hwaddr size) +{ + DeviceState *dev =3D qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); + MemoryRegion *mr_dev; + + qdev_prop_set_string(dev, "name", name); + qdev_prop_set_uint64(dev, "size", size); + object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); + qdev_init_nofail(dev); + + mr_dev =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(mr, base, mr_dev); +} + +static void versal_unimp(Versal *s) +{ + versal_unimp_area(s, "psm", &s->mr_ps, + MM_PSM_START, MM_PSM_END - MM_PSM_START); + versal_unimp_area(s, "crl", &s->mr_ps, + MM_CRL, MM_CRL_SIZE); + versal_unimp_area(s, "crf", &s->mr_ps, + MM_FPD_CRF, MM_FPD_CRF_SIZE); + versal_unimp_area(s, "iou-scntr", &s->mr_ps, + MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); + versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, + MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); +} + +static void versal_realize(DeviceState *dev, Error **errp) +{ + Versal *s =3D XLNX_VERSAL(dev); + qemu_irq pic[XLNX_VERSAL_NR_IRQS]; + + versal_create_apu_cpus(s, errp); + versal_create_apu_gic(s, pic, errp); + versal_create_uarts(s, pic); + versal_create_gems(s, pic); + versal_map_ddr(s); + versal_unimp(s); + + /* Create the OCM. */ + memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", + MM_OCM_SIZE, &error_fatal); + + memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm,= 0); + memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); +} + +static void versal_init(Object *obj) +{ + Versal *s =3D XLNX_VERSAL(obj); + + memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); + memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); +} + +static const VMStateDescription versal_vmstate =3D { + .name =3D "xlnx-ve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + /* FIXME. */ + VMSTATE_END_OF_LIST() + } +}; + +static Property versal_properties[] =3D { + DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void versal_reset(DeviceState *dev) +{ +} + +static void versal_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D versal_realize; + dc->vmsd =3D &versal_vmstate; + dc->props =3D versal_properties; + dc->reset =3D versal_reset; +} + +static const TypeInfo versal_info =3D { + .name =3D TYPE_XLNX_VERSAL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Versal), + .instance_init =3D versal_init, + .class_init =3D versal_class_init, +}; + +static void versal_register_types(void) +{ + type_register_static(&versal_info); +} + +type_init(versal_register_types); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h new file mode 100644 index 0000000..9da621e --- /dev/null +++ b/include/hw/arm/xlnx-versal.h @@ -0,0 +1,122 @@ +/* + * Model of the Xilinx Versal + * + * Copyright (c) 2018 Xilinx Inc. + * Written by Edgar E. Iglesias + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#ifndef XLNX_VERSAL_H +#define XLNX_VERSAL_H + +#include "hw/sysbus.h" +#include "hw/arm/arm.h" +#include "hw/intc/arm_gicv3.h" + +#define TYPE_XLNX_VERSAL "xlnx-versal" +#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) + +#define XLNX_VERSAL_NR_ACPUS 2 +#define XLNX_VERSAL_NR_UARTS 2 +#define XLNX_VERSAL_NR_GEMS 2 +#define XLNX_VERSAL_NR_IRQS 256 + +typedef struct Versal { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + struct { + struct { + MemoryRegion mr; + ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; + GICv3State gic; + } apu; + } fpd; + + MemoryRegion mr_ps; + + struct { + /* 4 ranges to access DDR. */ + MemoryRegion mr_ddr_ranges[4]; + } noc; + + struct { + MemoryRegion mr_ocm; + + struct { + SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; + SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; + } iou; + } lpd; + + struct { + MemoryRegion *mr_ddr; + uint32_t psci_conduit; + } cfg; +} Versal; + +/* Memory-map and IRQ definitions. Copied a subset from + * auto-generated files. */ + +#define VERSAL_GIC_MAINT_IRQ 9 +#define VERSAL_TIMER_VIRT_IRQ 11 +#define VERSAL_TIMER_S_EL1_IRQ 13 +#define VERSAL_TIMER_NS_EL1_IRQ 14 +#define VERSAL_TIMER_NS_EL2_IRQ 10 + +#define VERSAL_UART0_IRQ_0 18 +#define VERSAL_UART1_IRQ_0 19 +#define VERSAL_GEM0_IRQ_0 56 +#define VERSAL_GEM0_WAKE_IRQ_0 57 +#define VERSAL_GEM1_IRQ_0 58 +#define VERSAL_GEM1_WAKE_IRQ_0 59 + +/* Architecturally eserved IRQs suitable for virtualization. */ +#define VERSAL_RSVD_HIGH_IRQ_FIRST 160 +#define VERSAL_RSVD_HIGH_IRQ_LAST 255 + +#define MM_TOP_RSVD 0xa0000000U +#define MM_TOP_RSVD_SIZE 0x4000000 +#define MM_GIC_APU_DIST_MAIN 0xf9000000U +#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 +#define MM_GIC_APU_REDIST_0 0xf9080000U +#define MM_GIC_APU_REDIST_0_SIZE 0x80000 + +#define MM_UART0 0xff000000U +#define MM_UART0_SIZE 0x10000 +#define MM_UART1 0xff010000U +#define MM_UART1_SIZE 0x10000 + +#define MM_GEM0 0xff0c0000U +#define MM_GEM0_SIZE 0x10000 +#define MM_GEM1 0xff0d0000U +#define MM_GEM1_SIZE 0x10000 + +#define MM_OCM 0xfffc0000U +#define MM_OCM_SIZE 0x40000 + +#define MM_TOP_DDR 0x0 +#define MM_TOP_DDR_SIZE 0x80000000U +#define MM_TOP_DDR_2 0x800000000ULL +#define MM_TOP_DDR_2_SIZE 0x800000000ULL +#define MM_TOP_DDR_3 0xc000000000ULL +#define MM_TOP_DDR_3_SIZE 0x4000000000ULL +#define MM_TOP_DDR_4 0x10000000000ULL +#define MM_TOP_DDR_4_SIZE 0xb780000000ULL + +#define MM_PSM_START 0xffc80000U +#define MM_PSM_END 0xffcf0000U + +#define MM_CRL 0xff5e0000U +#define MM_CRL_SIZE 0x300000 +#define MM_IOU_SCNTR 0xff130000U +#define MM_IOU_SCNTR_SIZE 0x10000 +#define MM_IOU_SCNTRS 0xff140000U +#define MM_IOU_SCNTRS_SIZE 0x10000 +#define MM_FPD_CRF 0xfd1a0000U +#define MM_FPD_CRF_SIZE 0x140000 +#endif --=20 2.7.4 From nobody Sun May 5 18:16:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v1 12/12] hw/arm: versal: Add a virtual Xilinx Versal board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add a virtual Xilinx Versal board. This board is based on the Xilinx Versal SoC. The exact details of what peripherals are attached to this board will remain in control of QEMU. QEMU will generate an FDT on the fly for Linux and other software to auto-discover peripherals. Signed-off-by: Edgar E. Iglesias --- hw/arm/Makefile.objs | 2 +- hw/arm/xlnx-versal-virt.c | 494 ++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 495 insertions(+), 1 deletion(-) create mode 100644 hw/arm/xlnx-versal-virt.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index ec21d9b..50c7b4a 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -26,7 +26,7 @@ obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboa= rd.o obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zynqmp.o xlnx-zcu102.o -obj-$(CONFIG_XLNX_VERSAL) +=3D xlnx-versal.o +obj-$(CONFIG_XLNX_VERSAL) +=3D xlnx-versal.o xlnx-versal-virt.o obj-$(CONFIG_FSL_IMX25) +=3D fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c new file mode 100644 index 0000000..1ae125b --- /dev/null +++ b/hw/arm/xlnx-versal-virt.c @@ -0,0 +1,494 @@ +/* + * Xilinx Versal Virtual board. + * + * Copyright (c) 2018 Xilinx Inc. + * Written by Edgar E. Iglesias + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "sysemu/device_tree.h" +#include "exec/address-spaces.h" +#include "hw/boards.h" +#include "hw/sysbus.h" +#include "hw/arm/sysbus-fdt.h" +#include "hw/arm/fdt.h" +#include "cpu.h" +#include "hw/arm/xlnx-versal.h" + +#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") +#define XLNX_VERSAL_VIRT_MACHINE(obj) \ + OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE) + +typedef struct VersalVirt { + MachineState parent_obj; + + Versal soc; + MemoryRegion mr_ddr; + + void *fdt; + int fdt_size; + struct { + uint32_t gic; + uint32_t ethernet_phy[2]; + uint32_t clk_125Mhz; + uint32_t clk_25Mhz; + } phandle; + struct arm_boot_info binfo; + + struct { + bool secure; + } cfg; +} VersalVirt; + +static void fdt_create(VersalVirt *s) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(s); + int i; + + s->fdt =3D create_device_tree(&s->fdt_size); + if (!s->fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + /* Allocate all phandles. */ + s->phandle.gic =3D qemu_fdt_alloc_phandle(s->fdt); + for (i =3D 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { + s->phandle.ethernet_phy[i] =3D qemu_fdt_alloc_phandle(s->fdt); + } + s->phandle.clk_25Mhz =3D qemu_fdt_alloc_phandle(s->fdt); + s->phandle.clk_125Mhz =3D qemu_fdt_alloc_phandle(s->fdt); + + /* Create /chosen node for load_dtb. */ + qemu_fdt_add_subnode(s->fdt, "/chosen"); + + /* Header */ + qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); + qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); + qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); +} + +static void fdt_add_clk_node(VersalVirt *s, const char *name, + unsigned int freq_hz, uint32_t phandle) +{ + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); + qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); + qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); + qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); + qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); +} + +static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) +{ + int i; + + qemu_fdt_add_subnode(s->fdt, "/cpus"); + qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); + + for (i =3D XLNX_VERSAL_NR_ACPUS - 1; i >=3D 0; i--) { + char *name =3D g_strdup_printf("/cpus/cpu@%d", i); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); + if (psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { + qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); + } + qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); + qemu_fdt_setprop_string(s->fdt, name, "compatible", + armcpu->dtb_compatible); + g_free(name); + } +} + +static void fdt_add_gic_nodes(VersalVirt *s) +{ + char *nodename; + + nodename =3D g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); + qemu_fdt_add_subnode(s->fdt, nodename); + qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); + qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + 2, MM_GIC_APU_DIST_MAIN, + 2, MM_GIC_APU_DIST_MAIN_SIZE, + 2, MM_GIC_APU_REDIST_0, + 2, MM_GIC_APU_REDIST_0_SIZE); + qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); + qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); +} + +static void fdt_add_timer_nodes(VersalVirt *s) +{ + const char compat[] =3D "arm,armv8-timer"; + uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; + + qemu_fdt_add_subnode(s->fdt, "/timer"); + qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); + qemu_fdt_setprop(s->fdt, "/timer", "compatible", + compat, sizeof(compat)); +} + +static void fdt_add_uart_nodes(VersalVirt *s) +{ + uint64_t addrs[] =3D { MM_UART1, MM_UART0 }; + unsigned int irqs[] =3D { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; + const char compat[] =3D "arm,pl011\0arm,sbsa-uart"; + const char clocknames[] =3D "uartclk\0apb_pclk"; + int i; + + for (i =3D 0; i < ARRAY_SIZE(addrs); i++) { + char *name =3D g_strdup_printf("/uart@%" PRIx64, addrs[i]); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_125Mhz, s->phandle.clk_125Mh= z); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irqs[i], + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, addrs[i], 2, 0x1000); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); + + if (addrs[i] =3D=3D MM_UART0) { + /* Select UART0. */ + qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name= ); + } + g_free(name); + } +} + +static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, + uint32_t phandle) +{ + char *name =3D g_strdup_printf("%s/fixed-link", gemname); + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); + qemu_fdt_setprop_cells(s->fdt, name, "full-duplex"); + qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); + g_free(name); +} + +static void fdt_add_gem_nodes(VersalVirt *s) +{ + uint64_t addrs[] =3D { MM_GEM1, MM_GEM0 }; + unsigned int irqs[] =3D { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; + const char clocknames[] =3D "pclk\0hclk\0tx_clk\0rx_clk"; + const char compat_gem[] =3D "cdns,zynqmp-gem\0cdns,gem"; + int i; + + for (i =3D 0; i < ARRAY_SIZE(addrs); i++) { + char *name =3D g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); + qemu_fdt_add_subnode(s->fdt, name); + + fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); + qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); + qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", + s->phandle.ethernet_phy[i]); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, + s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irqs[i], + GIC_FDT_IRQ_FLAGS_LEVEL_HI, + GIC_FDT_IRQ_TYPE_SPI, irqs[i], + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, addrs[i], 2, 0x1000); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat_gem, sizeof(compat_gem)); + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); + g_free(name); + } +} + +static void fdt_nop_memory_nodes(void *fdt, Error **errp) +{ + Error *err =3D NULL; + char **node_path; + int n =3D 0; + + node_path =3D qemu_fdt_node_unit_path(fdt, "memory", &err); + if (err) { + error_propagate(errp, err); + return; + } + while (node_path[n]) { + if (g_str_has_prefix(node_path[n], "/memory")) { + qemu_fdt_nop_node(fdt, node_path[n]); + } + n++; + } + g_strfreev(node_path); +} + +static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_si= ze) +{ + /* Describes the various split DDR access regions. */ + static const struct { + uint64_t base; + uint64_t size; + } addr_ranges[] =3D { + { MM_TOP_DDR, MM_TOP_DDR_SIZE }, + { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, + { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, + { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } + }; + uint64_t mem_reg_prop[8] =3D {0}; + uint64_t size =3D ram_size; + Error *err =3D NULL; + char *name; + int i; + + fdt_nop_memory_nodes(fdt, &err); + if (err) { + error_report_err(err); + return; + } + + name =3D g_strdup_printf("/memory@%x", MM_TOP_DDR); + for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { + uint64_t mapsize; + + mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; + + mem_reg_prop[i * 2] =3D addr_ranges[i].base; + mem_reg_prop[i * 2 + 1] =3D mapsize; + size -=3D mapsize; + } + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); + + switch (i) { + case 1: + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, mem_reg_prop[0], + 2, mem_reg_prop[1]); + break; + case 2: + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, mem_reg_prop[0], + 2, mem_reg_prop[1], + 2, mem_reg_prop[2], + 2, mem_reg_prop[3]); + break; + case 3: + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, mem_reg_prop[0], + 2, mem_reg_prop[1], + 2, mem_reg_prop[2], + 2, mem_reg_prop[3], + 2, mem_reg_prop[4], + 2, mem_reg_prop[5]); + break; + case 4: + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, mem_reg_prop[0], + 2, mem_reg_prop[1], + 2, mem_reg_prop[2], + 2, mem_reg_prop[3], + 2, mem_reg_prop[4], + 2, mem_reg_prop[5], + 2, mem_reg_prop[6], + 2, mem_reg_prop[7]); + break; + default: + g_assert_not_reached(); + } + g_free(name); +} + +static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, + void *fdt) +{ + VersalVirt *s =3D container_of(binfo, VersalVirt, binfo); + + fdt_add_memory_nodes(s, fdt, binfo->ram_size); +} + +static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, + int *fdt_size) +{ + const VersalVirt *board =3D container_of(binfo, VersalVirt, binfo); + + *fdt_size =3D board->fdt_size; + return board->fdt; +} + +#define NUM_VIRTIO_TRANSPORT 32 +static void create_virtio_regions(VersalVirt *s) +{ + int virtio_mmio_size =3D 0x200; + int i; + + for (i =3D 0; i < NUM_VIRTIO_TRANSPORT; i++) { + char *name =3D g_strdup_printf("virtio%d", i);; + hwaddr base =3D MM_TOP_RSVD + i * virtio_mmio_size; + int irq =3D VERSAL_RSVD_HIGH_IRQ_FIRST + i; + MemoryRegion *mr; + DeviceState *dev; + qemu_irq pic_irq; + + pic_irq =3D qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); + dev =3D qdev_create(NULL, "virtio-mmio"); + object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev), + &error_fatal); + qdev_init_nofail(dev); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->soc.mr_ps, base, mr); + sysbus_create_simple("virtio-mmio", base, pic_irq); + } + + for (i =3D 0; i < NUM_VIRTIO_TRANSPORT; i++) { + hwaddr base =3D MM_TOP_RSVD + i * virtio_mmio_size; + int irq =3D VERSAL_RSVD_HIGH_IRQ_FIRST + i; + char *name =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, base, 2, virtio_mmio_size); + qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); + g_free(name); + } +} + +static void versal_virt_init(MachineState *machine) +{ + VersalVirt *s =3D XLNX_VERSAL_VIRT_MACHINE(machine); + int psci_conduit =3D QEMU_PSCI_CONDUIT_DISABLED; + + /* + * If the user provides an Operating System to be loaded, we expect th= em + * to use the -kernel command line option. + * + * Users can load firmware or boot-loaders with the -device loader opt= ions. + * + * When loading an OS, we generate a dtb and let arm_load_kernel() sel= ect + * where it gets loaded. This dtb will be passed to the kernel in x0. + * + * If there's no -kernel option, we generate a DTB and place it at 0x1= 000 + * for the bootloaders or firmware to pick up. + * + * If users want to provide their own DTB, they can use the -dtb optio= n. + * These dtb's will have their memory nodes modified to match QEMU's + * selected ram_size option before they get passed to the kernel or fw. + * + * When loading an OS, we turn on QEMU's PSCI implementation with SMC + * as the PSCI conduit. When there's no -kernel, we assume the user + * provides EL3 firmware to handle PSCI. + */ + if (machine->kernel_filename) { + psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + } + + memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr", + machine->ram_size); + + sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc, + sizeof(s->soc), TYPE_XLNX_VERSAL); + object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr), + "ddr", &error_abort); + object_property_set_int(OBJECT(&s->soc), psci_conduit, + "psci-conduit", &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fat= al); + + fdt_create(s); + create_virtio_regions(s); + fdt_add_gem_nodes(s); + fdt_add_uart_nodes(s); + fdt_add_gic_nodes(s); + fdt_add_timer_nodes(s); + fdt_add_cpu_nodes(s, psci_conduit); + fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); + fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); + + /* Make the APU cpu address space visible to virtio and other + * modules unaware of muliple address-spaces. */ + memory_region_add_subregion_overlap(get_system_memory(), + 0, &s->soc.fpd.apu.mr, 0); + + s->binfo.ram_size =3D machine->ram_size; + s->binfo.kernel_filename =3D machine->kernel_filename; + s->binfo.kernel_cmdline =3D machine->kernel_cmdline; + s->binfo.initrd_filename =3D machine->initrd_filename; + s->binfo.loader_start =3D 0x0; + s->binfo.get_dtb =3D versal_virt_get_dtb; + s->binfo.modify_dtb =3D versal_virt_modify_dtb; + if (machine->kernel_filename) { + arm_load_kernel(s->soc.fpd.apu.cpu[0], &s->binfo); + } else { + AddressSpace *as =3D arm_boot_address_space(s->soc.fpd.apu.cpu[0], + &s->binfo); + /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (N= ULL). + * Offset things by 4K. */ + s->binfo.loader_start =3D 0x1000; + s->binfo.dtb_limit =3D 0x1000000; + if (arm_load_dtb(s->binfo.loader_start, + &s->binfo, s->binfo.dtb_limit, as) < 0) { + exit(EXIT_FAILURE); + } + } +} + +static void versal_virt_machine_instance_init(Object *obj) +{ +} + +static void versal_virt_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Xilinx Versal Virtual development board"; + mc->init =3D versal_virt_init; + mc->max_cpus =3D XLNX_VERSAL_NR_ACPUS; + mc->default_cpus =3D XLNX_VERSAL_NR_ACPUS; + mc->no_cdrom =3D true; +} + +static const TypeInfo versal_virt_machine_init_typeinfo =3D { + .name =3D TYPE_XLNX_VERSAL_VIRT_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D versal_virt_machine_class_init, + .instance_init =3D versal_virt_machine_instance_init, + .instance_size =3D sizeof(VersalVirt), +}; + +static void versal_virt_machine_init_register_types(void) +{ + type_register_static(&versal_virt_machine_init_typeinfo); +} + +type_init(versal_virt_machine_init_register_types) + --=20 2.7.4