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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 19/79] hw/char/sh_serial: Add timeout handling to unbreak serial input X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Geert Uytterhoeven Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Geert Uytterhoeven As of commit 18e8cf159177100e ("serial: sh-sci: increase RX FIFO trigger defaults for (H)SCIF") in Linux v4.11-rc1, the serial console on the QEMU SH4 target is broken: it delays serial input until enough data has been received. Since aforementioned commit, the Linux SCIF driver programs the Receive FIFO Data Count Trigger bits in the FIFO Control Register, to postpone generating a receive interrupt until: 1. At least the receive trigger count of bytes of data are available in the receive FIFO, OR 2. No further data has been received for at least 15 etu after the last received data. While QEMU implements the former, it does not implement the latter. Hence the receive interrupt is not generated until the former condition is met. Fix this by adding basic timeout handling. As the QEMU SCIF emulation ignores any serial speed programming, the timeout value used conforms to a default speed of 9600 bps, which is fine for any interactive console. Reported-by: Rob Landley Signed-off-by: Geert Uytterhoeven Tested-by: Ulrich Hecht Tested-by: Rob Landley Tested-by: Rich Felker Message-Id: <20180905131125.12635-1-geert+renesas@glider.be> Signed-off-by: Paolo Bonzini --- hw/char/sh_serial.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 373a405..1283156 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -29,6 +29,7 @@ #include "hw/sh4/sh.h" #include "chardev/char-fe.h" #include "qapi/error.h" +#include "qemu/timer.h" =20 //#define DEBUG_SERIAL =20 @@ -63,6 +64,8 @@ typedef struct { int rtrg; =20 CharBackend chr; + QEMUTimer *fifo_timeout_timer; + uint64_t etu; /* Elementary Time Unit (ns) */ =20 qemu_irq eri; qemu_irq rxi; @@ -314,6 +317,16 @@ static int sh_serial_can_receive1(void *opaque) return sh_serial_can_receive(s); } =20 +static void sh_serial_timeout_int(void *opaque) +{ + sh_serial_state *s =3D opaque; + + s->flags |=3D SH_SERIAL_FLAG_RDF; + if (s->scr & (1 << 6) && s->rxi) { + qemu_set_irq(s->rxi, 1); + } +} + static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) { sh_serial_state *s =3D opaque; @@ -330,8 +343,12 @@ static void sh_serial_receive1(void *opaque, const uin= t8_t *buf, int size) if (s->rx_cnt >=3D s->rtrg) { s->flags |=3D SH_SERIAL_FLAG_RDF; if (s->scr & (1 << 6) && s->rxi) { + timer_del(s->fifo_timeout_timer); qemu_set_irq(s->rxi, 1); } + } else { + timer_mod(s->fifo_timeout_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->et= u); } } } @@ -402,6 +419,9 @@ void sh_serial_init(MemoryRegion *sysmem, sh_serial_event, NULL, s, NULL, true); } =20 + s->fifo_timeout_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sh_serial_timeout_int, s); + s->etu =3D NANOSECONDS_PER_SECOND / 9600; s->eri =3D eri_source; s->rxi =3D rxi_source; s->txi =3D txi_source; --=20 1.8.3.1