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[45.78.72.26]) by smtp.gmail.com with ESMTPSA id 87-v6sm21276632pfn.103.2018.09.17.07.57.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 07:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hxDCg9nGxPANRMfHzgt6OvPgSuuab0QtkxB8S1Slfe8=; b=EvTTyLJtXuoAQiE/k9xdfo2wfkNAg/Ns9txjuTIJv1+VpuKeBC79078nzJQETHPLIE 9MsNNwmIQOD/N3C9jKYPBW+mSk0u7gJm2TQ2t0FKVccea6P/Th/VuH37N4BifGvoiBDC E+Ye7RW4XHSb+r+jk5VfD8vFwbUPwOauf3t9pU4yt5SuGzasumVRuLSxrzreAXmcj+bq h3947PHvjzSVCLVtYsKT2zd9MPYXIJ2IJlkJ5rHNAFuUIkF2LKCn1waDGiQRqR4SXD8d qW/sYhZkMPCAnMD3VoRwLUqmpeWX93tZEXOPWdOekhC46dGd6spX5t/OfF+OG7xvaH/7 6Wzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hxDCg9nGxPANRMfHzgt6OvPgSuuab0QtkxB8S1Slfe8=; b=eSyVf6x8JEo9mlbwoZEmmE+M9uOKWNF5OtcrN8vH0cqGttGOZoAsHAp7YvUerY9np9 HHW0NQB7iJxd2wdWmlbVZQSHxXA1xwQiLVpqrjyQMU8vYP6fDStajhY+vFoK/ms38iwl Na3IR2T4bazBVsFsT9ojd4DfjNhqc0zIIaJODAakLMwAwuj/h/J+JOfRu7/KKRSsedp6 HhFQrF+7xG8OFZFJlX8Vd1/uSdmiI4kXx2xvuG6TCQP71CiXGFymPXqTfcwP65sLCx/5 rwSTD9R5dNd11shhfe/b72GmuVZZ1tS0BC6UAJsqMYwKw+9i5PDEiXNFDI2kQEW07Mja f4Bw== X-Gm-Message-State: APzg51CJLeSINtrYpmw6kbqBXN8Ve9hARQMWEhxyNw0C9lqM/7e5Ikvx gk8/5MymMIrFO+34jCMOPf0JsDjQ6aE= X-Google-Smtp-Source: ANB0VdZLyUeTGLgx5JST/IwCpP6+JPYBFWUAVZgmRX3krmMMmkU47aL7LtweS6cCciHax9Pqs0Q9FA== X-Received: by 2002:a62:9bc9:: with SMTP id e70-v6mr25840818pfk.95.1537196279564; Mon, 17 Sep 2018 07:57:59 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 22:57:32 +0800 Message-Id: <1537196258-12581-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [RFC v5 1/6] pci_expander_bridge: add type TYPE_PXB_PCIE_HOST X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default, add a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 86 +++++++++++++++++++++++++++++++++= ++-- 1 file changed, 82 insertions(+), 4 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index e62de42..a052c4c 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -15,10 +15,12 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_host.h" #include "hw/pci/pci_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" +#include "qapi/visitor.h" =20 #define TYPE_PXB_BUS "pxb-bus" #define PXB_BUS(obj) OBJECT_CHECK(PXBBus, (obj), TYPE_PXB_BUS) @@ -40,6 +42,9 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 +#define PROP_PXB_BUS_NR "bus_nr" +#define PROP_PXB_NUMA_NODE "numa_node" + typedef struct PXBDev { /*< private >*/ PCIDevice parent_obj; @@ -49,6 +54,16 @@ typedef struct PXBDev { uint16_t numa_node; } PXBDev; =20 +#define TYPE_PXB_PCIE_HOST "pxb-pcie-host" +#define PXB_PCIE_HOST_DEVICE(obj) \ + OBJECT_CHECK(PXBPCIEHost, (obj), TYPE_PXB_PCIE_HOST) + +typedef struct PXBPCIEHost { + /*< private >*/ + PCIExpressHost parent_obj; + /*< public >*/ +} PXBPCIEHost; + static PXBDev *convert_to_pxb(PCIDevice *dev) { return pci_bus_is_express(pci_get_bus(dev)) @@ -142,6 +157,40 @@ static char *pxb_host_ofw_unit_address(const SysBusDev= ice *dev) return NULL; } =20 +static void pxb_pcie_host_get_mmcfg_base(Object *obj, Visitor *v, const ch= ar *name, + void *opaque, Error **errp) +{ + PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); + + visit_type_uint64(v, name, &e->size, errp); +} + +static void pxb_pcie_host_get_mmcfg_size(Object *obj, Visitor *v, const ch= ar *name, + void *opaque, Error **errp) +{ + PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); + + visit_type_uint64(v, name, &e->size, errp); +} + +static void pxb_pcie_host_initfn(Object *obj) +{ + PCIHostState *phb =3D PCI_HOST_BRIDGE(obj); + + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, + "pci-conf-idx", 4); + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, + "pci-conf-data", 4); + + object_property_add(obj, PCIE_HOST_MCFG_BASE, "uint64", + pxb_pcie_host_get_mmcfg_base, + NULL, NULL, NULL, NULL); + + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", + pxb_pcie_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); +} + static void pxb_host_class_init(ObjectClass *class, void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); @@ -161,6 +210,27 @@ static const TypeInfo pxb_host_info =3D { .class_init =3D pxb_host_class_init, }; =20 +static void pxb_pcie_host_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(class); + SysBusDeviceClass *sbc =3D SYS_BUS_DEVICE_CLASS(class); + PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(class); + + dc->fw_name =3D "pcie"; + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by its= elf */ + dc->user_creatable =3D false; + sbc->explicit_ofw_unit_address =3D pxb_host_ofw_unit_address; + hc->root_bus_path =3D pxb_host_root_bus_path; +} + +static const TypeInfo pxb_pcie_host_info =3D { + .name =3D TYPE_PXB_PCIE_HOST, + .parent =3D TYPE_PCIE_HOST_BRIDGE, + .instance_size =3D sizeof(PXBPCIEHost), + .instance_init =3D pxb_pcie_host_initfn, + .class_init =3D pxb_pcie_host_class_init, +}; + /* * Registers the PXB bus as a child of pci host root bus. */ @@ -228,10 +298,11 @@ static void pxb_dev_realize_common(PCIDevice *dev, bo= ol pcie, Error **errp) dev_name =3D dev->qdev.id; } =20 - ds =3D qdev_create(NULL, TYPE_PXB_HOST); if (pcie) { + ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else { + ds =3D qdev_create(NULL, TYPE_PXB_HOST); bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_create(BUS(bus), "pci-bridge"); bds->id =3D dev_name; @@ -289,8 +360,14 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev) =20 static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ - DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), - DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), + DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), + DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), + DEFINE_PROP_END_OF_LIST(), +}; + +static Property pxb_pcie_dev_properties[] =3D { + DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), + DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -344,7 +421,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass,= void *data) k->class_id =3D PCI_CLASS_BRIDGE_HOST; =20 dc->desc =3D "PCI Express Expander Bridge"; - dc->props =3D pxb_dev_properties; + dc->props =3D pxb_pcie_dev_properties; dc->hotpluggable =3D false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -365,6 +442,7 @@ static void pxb_register_types(void) type_register_static(&pxb_bus_info); type_register_static(&pxb_pcie_bus_info); type_register_static(&pxb_host_info); + type_register_static(&pxb_pcie_host_info); type_register_static(&pxb_dev_info); type_register_static(&pxb_pcie_dev_info); } --=20 2.7.4 From nobody Sat Feb 7 04:01:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[45.78.72.26]) by smtp.gmail.com with ESMTPSA id 87-v6sm21276632pfn.103.2018.09.17.07.57.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 07:58:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V8HFlbUXWM+0DZy9scLdpuQ3+h0czUUsRr3yKnupDhM=; b=WIAlkzHUWL8xgxtUfAWUlhg3z2B+vXNyki43zT1VYPclR2noZ22PhUPUX3ErESv9ub yOhG4zUh7Ok25S4F7i6Ccmn1ViI7PfP2pnoNfhgOlfVzwQ+Qr7LID58xUawp01KOzTxi hHw0TtkxXVGKHQwTt3yeAYunN+UL55wFulygKHQKTXBcrJKAnc5cCOCALMsesqUmoZuy RWGR84dQ4nNAwsxigzJkT5rZ9atmt0fufLdq/1ZK6uLx4FEHzObdSvHh3Vv46NLze4p3 k95bcCqb0SAF2RCbm/2IIg1BmIWJzIHSYpVhPT3a3LtUUQB7/Yhb/5kYOhhouD5cEarI Jrdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V8HFlbUXWM+0DZy9scLdpuQ3+h0czUUsRr3yKnupDhM=; b=e7nUplrumU9KRwsyym0nIjz+h7aRyYG6IZBNdTb5xd8zYMmy6OWyUxE5Lu7qr7yvZy 27F+akb6QPm5wcPTUkRIzhuuK/BtQW7JYwKWWEQEgKaRxgAJuumqoFAc0AfHsNtuYZte MPDtVYoKO8Sc62Q5AgFbRZg5JCD0vOzoevhQV4+lsFGKbUA+lFMif0BhNXrnHe4aRNJ/ kvAoA15CEXpPhfStOfkrrJ+cjxmG3Do3nlJD5/sw4eWbKXdIxeNZuVCCRi6cSRRWNvQx jopAxOlHX98OD7IARsrLyuRVuzNGPZ0XwGbCbcT6owWe86dOsUYuU+O9qE1NF2XxkrOu SJjQ== X-Gm-Message-State: APzg51D2jIDtWnP1upMYsO6eZbbLPZ8Jg9ZJYX2p4lgr7KKU8nVCV3+n 38GanQuVxaZKZm2+W3acQvFzVCBEs5M= X-Google-Smtp-Source: ANB0VdbM6IZAvzgTliS3VtpHRftwe7k8n8ULPe9cJNUWFvqnIZv9Ajs97zJpEjF+JpohY6VHkG5bpQ== X-Received: by 2002:a63:c20:: with SMTP id b32-v6mr23794536pgl.400.1537196281692; Mon, 17 Sep 2018 07:58:01 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 22:57:33 +0800 Message-Id: <1537196258-12581-3-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [RFC v5 2/6] pci_expander_bridge: add domain_nr and max_bus property for pxb-pcie X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pxb-pcie resides in pci domain 0 by default and users can not specify the domain number. This patch adds 2 new property 'domain_nr' and 'max_bus' to pxb-pcie device. The first property allows user to choose a non-zero pci domain so that they can hopefully add more pcie devices without being restricted by the 256 bus number of a single pci domain. The second property max_bus allows user to specify the desired busses to be used in the new domain. Since each pcie bus needs 1MB config space, a full pci domain occupies 256MB, which is quite expensive. But most times user may only want a sub-range of busses(e.g. [3,9]), this is when max_bus becomes useful. By reducing the memory each domain consumes, we can support more domains in a limited space. Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index a052c4c..20fec50 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -42,6 +42,8 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 +#define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" +#define PROP_PXB_PCIE_MAX_BUS "max_bus" #define PROP_PXB_BUS_NR "bus_nr" #define PROP_PXB_NUMA_NODE "numa_node" =20 @@ -52,6 +54,8 @@ typedef struct PXBDev { =20 uint8_t bus_nr; uint16_t numa_node; + uint32_t domain_nr; /* PCI domain, non-zero means separate domain */ + uint8_t max_bus; /* max bus number to use(including this one) */ } PXBDev; =20 #define TYPE_PXB_PCIE_HOST "pxb-pcie-host" @@ -81,6 +85,14 @@ static int pxb_bus_num(PCIBus *bus) return pxb->bus_nr; } =20 +static int pxb_domain_num(PCIBus *bus) +{ + PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); + + /* for pxb, this should always be zero */ + return pxb->domain_nr; +} + static bool pxb_is_root(PCIBus *bus) { return true; /* by definition */ @@ -122,7 +134,7 @@ static const char *pxb_host_root_bus_path(PCIHostState = *host_bridge, PXBBus *bus =3D pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) : PXB_BUS(rootbus); =20 - snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus)); + snprintf(bus->bus_path, 8, "%04x:%02x", pxb_domain_num(rootbus), pxb_b= us_num(rootbus)); return bus->bus_path; } =20 @@ -275,7 +287,10 @@ static gint pxb_compare(gconstpointer a, gconstpointer= b) { const PXBDev *pxb_a =3D a, *pxb_b =3D b; =20 - return pxb_a->bus_nr < pxb_b->bus_nr ? -1 : + /* compare domain_nr first, then bus_nr */ + return pxb_a->domain_nr < pxb_b->domain_nr ? -1 : + pxb_a->domain_nr > pxb_b->domain_nr ? 1 : + pxb_a->bus_nr < pxb_b->bus_nr ? -1 : pxb_a->bus_nr > pxb_b->bus_nr ? 1 : 0; } @@ -299,6 +314,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) } =20 if (pcie) { + g_assert (pxb->domain_nr =3D=3D 0 || pxb->max_bus >=3D pxb->bus_nr= ); ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else { @@ -368,6 +384,9 @@ static Property pxb_dev_properties[] =3D { static Property pxb_pcie_dev_properties[] =3D { DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), + DEFINE_PROP_UINT32(PROP_PXB_PCIE_DOMAIN_NR, PXBDev, domain_nr, 0), + /* set a small default value, bus range is [bus_nr, max_bus] */ + DEFINE_PROP_UINT8(PROP_PXB_PCIE_MAX_BUS, PXBDev, max_bus, 15), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.7.4 From nobody Sat Feb 7 04:01:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1537196829204952.8065925125671; Mon, 17 Sep 2018 08:07:09 -0700 (PDT) Received: from localhost ([::1]:36017 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1v7D-0002QY-OD for importer@patchew.org; Mon, 17 Sep 2018 11:07:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1uyg-0004Zl-1A for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1uyY-00078e-Op for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:13 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g1uyW-00075R-F7 for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:10 -0400 Received: by mail-pf1-x442.google.com with SMTP id s13-v6so7686700pfi.7 for ; Mon, 17 Sep 2018 07:58:07 -0700 (PDT) Received: from biggerfish-TM1701.lan (45.78.72.26.16clouds.com. [45.78.72.26]) by smtp.gmail.com with ESMTPSA id 87-v6sm21276632pfn.103.2018.09.17.07.58.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 07:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xEy0sx36NyDyeGPDwuQ6IzYCbB3NU1/W1QRHPwTeeDk=; b=lc9XMhtNV+xu+8B3aqsW6hHU503zXBxbZsRNLmpSJtxPs5WPoC2CfkqS/dgc/p1Lvc TH7+ovWsdkHeshFX/0k8klG0JtpwSvjcU48Mo4n6gT3FIf4J8I61TRGkqpkXWJuW1j9y +hGS7tZznzotvCp8cBRj5Z/ogiHC0PJnaxMzq11zZO1Mrvspnsi8I6/5behtkb0sQfgU bd2VQGxlrc520q6ysKKMOBCLkSZ0iKUf98JNOVUgtNtC94YlYUmd5vIVbl9hJbM1D1+F VgGGhVhdtgPYrEGwrxbqk2T7XSqokmf3CZP7i7ElOmZBskWuW7QlwnFQ8GybN7kI/tE7 GZcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xEy0sx36NyDyeGPDwuQ6IzYCbB3NU1/W1QRHPwTeeDk=; b=dFNfPWH4LncVBrO63s//VxdQ4BT9abLsDxNkgh5xLr28QY5hneEGXV8dYGgR5WiscY deiwg69YrF/Hvxf+v5MWvu8vB0nc+dO6MvoovK+6zEPzxv4pp1K5VXFpnt2S5o8L8/jn CAqfWl+ohfQX7GFNKlEhGufvTmGvJdSH1SXE8Rr8vLLIbE6CZAAH7cqH+fcf4gD1+EyI AhBCRqV7ajVBgk3WpDP01mds3edeomtM05BQe4Qk5/LdN/FR504TRiTe3jv8ulKZmeeM Yhd5XaRvlRY7p3FzGMcgYp1K2x0zQIUswIT/3qo1quI7VCdKjoTYKhGOpw9iR3S/oQQu COKw== X-Gm-Message-State: APzg51CE+RQ3BnnI53zzXAPtDSxXVfLpcxtlSr5+TvzCCkoRVlRZy/q1 AVO5onyeg9C7iy4erYbjy1ncHKnLimc= X-Google-Smtp-Source: ANB0VdYWpJy6l3/R2OMV1LN52jCsk3BSWdHT8HN3ruH4Jk2TMWTo3YaFhDSHh8E8vvsOdB4oR/DDnA== X-Received: by 2002:a63:2a0b:: with SMTP id q11-v6mr20902235pgq.36.1537196285527; Mon, 17 Sep 2018 07:58:05 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 22:57:34 +0800 Message-Id: <1537196258-12581-4-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [RFC v5 3/6] acpi-build: allocate mcfg for pxb-pcie host bridges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allocate new segment for pxb-pcie host bridges in MCFG table, and reserve corresponding MCFG space for them. This allows user-defined pxb-pcie host bridges to be placed in different pci domain than q35 host. The pci_host_bridges list is changed to be tail list to ensure the q35 host is always the first element when traversing the list, because q35 host is inserted beofre pxb-pcie hosts A few new callbacks are added to PCIBusClass to get domain number and max_bus property of a given PCIBus. Only pxb-pcie with a non-zero domain number will have an item in MCFG table, others will still reside in pci domain 0 under q35 host Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 109 +++++++++++++++++++++---= ---- hw/pci-bridge/pci_expander_bridge.c | 51 +++++++++---- hw/pci/pci.c | 30 +++++++- include/hw/pci-bridge/pci_expander_bridge.h | 16 ++++ include/hw/pci/pci.h | 2 + include/hw/pci/pci_bus.h | 2 + include/hw/pci/pci_host.h | 2 +- 7 files changed, 167 insertions(+), 45 deletions(-) create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index e1ee8ae..9b49b0e 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -55,6 +55,7 @@ #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/q35.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/i386/x86-iommu.h" =20 #include "hw/acpi/aml-build.h" @@ -89,6 +90,10 @@ typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; + uint32_t domain_nr; + uint8_t start_bus; + uint8_t end_bus; + QTAILQ_ENTRY(AcpiMcfgInfo) next; } AcpiMcfgInfo; =20 typedef struct AcpiPmInfo { @@ -119,6 +124,9 @@ typedef struct AcpiBuildPciBusHotplugState { bool pcihp_bridge_en; } AcpiBuildPciBusHotplugState; =20 +static QTAILQ_HEAD(, AcpiMcfgInfo) mcfg =3D + QTAILQ_HEAD_INITIALIZER(mcfg); + static void init_common_fadt_data(Object *o, AcpiFadtData *data) { uint32_t io =3D object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, N= ULL); @@ -2427,18 +2435,28 @@ build_srat(GArray *table_data, BIOSLinker *linker, = MachineState *machine) } =20 static void -build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) +build_mcfg_q35(GArray *table_data, BIOSLinker *linker) { - AcpiTableMcfg *mcfg; + AcpiTableMcfg *mcfg_tbl; const char *sig; - int len =3D sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); - - mcfg =3D acpi_data_push(table_data, len); - mcfg->allocation[0].address =3D cpu_to_le64(info->mcfg_base); - /* Only a single allocation so no need to play with segments */ - mcfg->allocation[0].pci_segment =3D cpu_to_le16(0); - mcfg->allocation[0].start_bus_number =3D 0; - mcfg->allocation[0].end_bus_number =3D PCIE_MMCFG_BUS(info->mcfg_size = - 1); + int len, count =3D 0; + AcpiMcfgInfo *info; + + QTAILQ_FOREACH(info, &mcfg, next) { + count++; + } + + len =3D sizeof(*mcfg_tbl) + count * sizeof(mcfg_tbl->allocation[0]); + + mcfg_tbl =3D acpi_data_push(table_data, len); + + count =3D 0; + QTAILQ_FOREACH(info, &mcfg, next) { + mcfg_tbl->allocation[count].address =3D cpu_to_le64(info->mcfg_bas= e); + mcfg_tbl->allocation[count].pci_segment =3D cpu_to_le16(info->doma= in_nr); + mcfg_tbl->allocation[count].start_bus_number =3D info->start_bus; + mcfg_tbl->allocation[count++].end_bus_number =3D info->end_bus; + } =20 /* MCFG is used for ECAM which can be enabled or disabled by guest. * To avoid table size changes (which create migration issues), @@ -2446,13 +2464,13 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *link= er, AcpiMcfgInfo *info) * but set the signature to a reserved value in this case. * ACPI spec requires OSPMs to ignore such tables. */ - if (info->mcfg_base =3D=3D PCIE_BASE_ADDR_UNMAPPED) { + if (QTAILQ_FIRST(&mcfg)->mcfg_base =3D=3D PCIE_BASE_ADDR_UNMAPPED) { /* Reserved signature: ignored by OSPM */ sig =3D "QEMU"; } else { sig =3D "MCFG"; } - build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL= ); + build_header(linker, table_data, (void *)mcfg_tbl, sig, len, 1, NULL, = NULL); } =20 /* @@ -2606,25 +2624,66 @@ struct AcpiBuildState { MemoryRegion *linker_mr; } AcpiBuildState; =20 -static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) +static inline void cleanup_mcfg(void) +{ + AcpiMcfgInfo *cfg, *tmp; + + QTAILQ_FOREACH_SAFE (cfg, &mcfg, next, tmp) { + QTAILQ_REMOVE(&mcfg, cfg, next); + free(cfg); + } +} + +static bool acpi_get_mcfg(void) { Object *pci_host; QObject *o; + AcpiMcfgInfo *info; + uint8_t bus_nr =3D 0, end_bus =3D 255; + uint32_t domain_nr =3D 0, mcfg_size =3D MCH_HOST_BRIDGE_PCIEXBAR_MAX; + uint64_t mcfg_base =3D MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; + PCIBus *bus; =20 pci_host =3D acpi_get_i386_pci_host(); g_assert(pci_host); =20 - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); - if (!o) { - return false; + while (pci_host) { + if (object_dynamic_cast(pci_host, TYPE_PXB_PCIE_HOST)) { + /* we are in pxb-pcie, overwrite default value */ + bus =3D PCI_HOST_BRIDGE(pci_host)->bus; + domain_nr =3D pci_bus_domain_num(bus); + if (domain_nr =3D=3D 0) { + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host),= next)); + continue; + } + + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BAS= E, NULL); + assert(o); + mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZ= E, NULL); + assert(o); + mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + bus_nr =3D pci_bus_num(bus); + domain_nr =3D pci_bus_domain_num(bus); + end_bus =3D pci_bus_max_bus(bus); + } + + info =3D g_new0(AcpiMcfgInfo, 1); + g_assert(info); + info->domain_nr =3D domain_nr; + info->start_bus =3D bus_nr; + info->end_bus =3D end_bus; + info->mcfg_base =3D mcfg_base; + info->mcfg_size =3D mcfg_size; + + QTAILQ_INSERT_TAIL(&mcfg, info, next); + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); } - mcfg->mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); =20 - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); - assert(o); - mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); return true; } =20 @@ -2637,7 +2696,6 @@ void acpi_build(AcpiBuildTables *tables, MachineState= *machine) unsigned facs, dsdt, rsdt, fadt; AcpiPmInfo pm; AcpiMiscInfo misc; - AcpiMcfgInfo mcfg; Range pci_hole, pci_hole64; uint8_t *u; size_t aml_len =3D 0; @@ -2718,10 +2776,11 @@ void acpi_build(AcpiBuildTables *tables, MachineSta= te *machine) build_slit(tables_blob, tables->linker); } } - if (acpi_get_mcfg(&mcfg)) { + if (acpi_get_mcfg()) { acpi_add_table(table_offsets, tables_blob); - build_mcfg_q35(tables_blob, tables->linker, &mcfg); + build_mcfg_q35(tables_blob, tables->linker); } + cleanup_mcfg(); if (x86_iommu_get_default()) { IommuType IOMMUType =3D x86_iommu_get_type(); if (IOMMUType =3D=3D TYPE_AMD) { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 20fec50..1e1999d 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -17,6 +17,7 @@ #include "hw/pci/pci_host.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci_bridge.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -58,16 +59,6 @@ typedef struct PXBDev { uint8_t max_bus; /* max bus number to use(including this one) */ } PXBDev; =20 -#define TYPE_PXB_PCIE_HOST "pxb-pcie-host" -#define PXB_PCIE_HOST_DEVICE(obj) \ - OBJECT_CHECK(PXBPCIEHost, (obj), TYPE_PXB_PCIE_HOST) - -typedef struct PXBPCIEHost { - /*< private >*/ - PCIExpressHost parent_obj; - /*< public >*/ -} PXBPCIEHost; - static PXBDev *convert_to_pxb(PCIDevice *dev) { return pci_bus_is_express(pci_get_bus(dev)) @@ -85,11 +76,17 @@ static int pxb_bus_num(PCIBus *bus) return pxb->bus_nr; } =20 -static int pxb_domain_num(PCIBus *bus) +static int pxb_max_bus(PCIBus *bus) +{ + PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); + + return pxb->max_bus; +} + +static uint32_t pxb_domain_num(PCIBus *bus) { PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); =20 - /* for pxb, this should always be zero */ return pxb->domain_nr; } =20 @@ -110,8 +107,10 @@ static void pxb_bus_class_init(ObjectClass *class, voi= d *data) PCIBusClass *pbc =3D PCI_BUS_CLASS(class); =20 pbc->bus_num =3D pxb_bus_num; + pbc->max_bus =3D pxb_max_bus; pbc->is_root =3D pxb_is_root; pbc->numa_node =3D pxb_bus_numa_node; + pbc->domain_num =3D pxb_domain_num; } =20 static const TypeInfo pxb_bus_info =3D { @@ -174,7 +173,17 @@ static void pxb_pcie_host_get_mmcfg_base(Object *obj, = Visitor *v, const char *na { PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); =20 - visit_type_uint64(v, name, &e->size, errp); + visit_type_uint64(v, name, &e->base_addr, errp); +} + +static void pxb_pcie_host_set_mmcfg_base(Object *obj, Visitor *v, const ch= ar *name, + void *opaque, Error **errp) +{ + PXBPCIEHost *host =3D PXB_PCIE_HOST_DEVICE(obj); + uint64_t value; + + visit_type_uint64(v, name, &value, errp); + host->parent_obj.base_addr =3D value; } =20 static void pxb_pcie_host_get_mmcfg_size(Object *obj, Visitor *v, const ch= ar *name, @@ -185,6 +194,16 @@ static void pxb_pcie_host_get_mmcfg_size(Object *obj, = Visitor *v, const char *na visit_type_uint64(v, name, &e->size, errp); } =20 +static void pxb_pcie_host_set_mmcfg_size(Object *obj, Visitor *v, const ch= ar *name, + void *opaque, Error **errp) +{ + PXBPCIEHost *host =3D PXB_PCIE_HOST_DEVICE(obj); + uint32_t value; + + visit_type_uint32(v, name, &value, errp); + host->parent_obj.size =3D value; +} + static void pxb_pcie_host_initfn(Object *obj) { PCIHostState *phb =3D PCI_HOST_BRIDGE(obj); @@ -196,11 +215,13 @@ static void pxb_pcie_host_initfn(Object *obj) =20 object_property_add(obj, PCIE_HOST_MCFG_BASE, "uint64", pxb_pcie_host_get_mmcfg_base, - NULL, NULL, NULL, NULL); + pxb_pcie_host_set_mmcfg_base, + NULL, NULL, NULL); =20 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", pxb_pcie_host_get_mmcfg_size, - NULL, NULL, NULL, NULL); + pxb_pcie_host_set_mmcfg_size, + NULL, NULL, NULL); } =20 static void pxb_host_class_init(ObjectClass *class, void *data) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 80bc459..fe69672 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -142,6 +142,15 @@ static int pcibus_num(PCIBus *bus) return bus->parent_dev->config[PCI_SECONDARY_BUS]; } =20 +/* return 0 unless user overwrite this callback */ +static uint32_t pcibus_domain_num(PCIBus *bus) { + return 0; +} + +static int pcibus_max_bus(PCIBus *bus) { + return 255; +} + static uint16_t pcibus_numa_node(PCIBus *bus) { return NUMA_NODE_UNASSIGNED; @@ -162,6 +171,8 @@ static void pci_bus_class_init(ObjectClass *klass, void= *data) pbc->is_root =3D pcibus_is_root; pbc->bus_num =3D pcibus_num; pbc->numa_node =3D pcibus_numa_node; + pbc->domain_num =3D pcibus_domain_num; + pbc->max_bus =3D pcibus_max_bus; } =20 static const TypeInfo pci_bus_info =3D { @@ -196,7 +207,8 @@ static void pci_del_option_rom(PCIDevice *pdev); static uint16_t pci_default_sub_vendor_id =3D PCI_SUBVENDOR_ID_REDHAT_QUMR= ANET; static uint16_t pci_default_sub_device_id =3D PCI_SUBDEVICE_ID_QEMU; =20 -static QLIST_HEAD(, PCIHostState) pci_host_bridges; +static QTAILQ_HEAD(, PCIHostState) pci_host_bridges =3D + QTAILQ_HEAD_INITIALIZER(pci_host_bridges); =20 int pci_bar(PCIDevice *d, int reg) { @@ -330,7 +342,7 @@ static void pci_host_bus_register(DeviceState *host) { PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(host); =20 - QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); + QTAILQ_INSERT_TAIL(&pci_host_bridges, host_bridge, next); } =20 PCIBus *pci_device_root_bus(const PCIDevice *d) @@ -444,6 +456,16 @@ int pci_bus_num(PCIBus *s) return PCI_BUS_GET_CLASS(s)->bus_num(s); } =20 +uint32_t pci_bus_domain_num(PCIBus *s) +{ + return PCI_BUS_GET_CLASS(s)->domain_num(s); +} + +int pci_bus_max_bus(PCIBus *s) +{ + return PCI_BUS_GET_CLASS(s)->max_bus(s); +} + int pci_bus_numa_node(PCIBus *bus) { return PCI_BUS_GET_CLASS(bus)->numa_node(bus); @@ -1798,7 +1820,7 @@ PciInfoList *qmp_query_pci(Error **errp) PciInfoList *info, *head =3D NULL, *cur_item =3D NULL; PCIHostState *host_bridge; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { info =3D g_malloc0(sizeof(*info)); info->value =3D qmp_query_pci_bus(host_bridge->bus, pci_bus_num(host_bridge->bus)); @@ -2493,7 +2515,7 @@ int pci_qdev_find_device(const char *id, PCIDevice **= pdev) PCIHostState *host_bridge; int rc =3D -ENODEV; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { int tmp =3D pci_qdev_find_recursive(host_bridge->bus, id, pdev); if (!tmp) { rc =3D 0; diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h new file mode 100644 index 0000000..e017c62 --- /dev/null +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -0,0 +1,16 @@ +#ifndef HW_PCI_EXPANDER_H +#define HW_PCI_EXPANDER_H + +#include "hw/pci/pcie_host.h" + +#define TYPE_PXB_PCIE_HOST "pxb-pcie-host" +#define PXB_PCIE_HOST_DEVICE(obj) \ + OBJECT_CHECK(PXBPCIEHost, (obj), TYPE_PXB_PCIE_HOST) + +typedef struct PXBPCIEHost { + /*< private >*/ + PCIExpressHost parent_obj; + /*< public >*/ +} PXBPCIEHost; + +#endif diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 990d6fc..b127fcf 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -436,6 +436,8 @@ static inline PCIBus *pci_get_bus(const PCIDevice *dev) return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); } int pci_bus_num(PCIBus *s); +uint32_t pci_bus_domain_num(PCIBus *s); +int pci_bus_max_bus(PCIBus *s); static inline int pci_dev_bus_num(const PCIDevice *dev) { return pci_bus_num(pci_get_bus(dev)); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index b7da8f5..faad155 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -15,7 +15,9 @@ typedef struct PCIBusClass { =20 bool (*is_root)(PCIBus *bus); int (*bus_num)(PCIBus *bus); + int (*max_bus)(PCIBus *bus); uint16_t (*numa_node)(PCIBus *bus); + uint32_t (*domain_num)(PCIBus *bus); } PCIBusClass; =20 struct PCIBus { diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..a5617cf 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -47,7 +47,7 @@ struct PCIHostState { uint32_t config_reg; PCIBus *bus; =20 - QLIST_ENTRY(PCIHostState) next; + QTAILQ_ENTRY(PCIHostState) next; }; =20 typedef struct PCIHostBridgeClass { --=20 2.7.4 From nobody Sat Feb 7 04:01:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [RFC v5 4/6] i386/acpi-build: describe new pci domain in AML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Describe new pci segments of host bridges in AML as new pci devices, with _SEG and _BBN to let them be in DSDT. Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 53 +++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9b49b0e..00b9aff 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1879,10 +1879,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 crs_range_set_init(&crs_range_set); bus =3D PC_MACHINE(machine)->bus; + i =3D 1; // PCI0 is q35 host, pxb starts from PCI1 if (bus) { QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num =3D pci_bus_num(bus); uint8_t numa_node =3D pci_bus_numa_node(bus); + uint32_t domain_num =3D pci_bus_domain_num(bus); =20 /* look only for expander root buses */ if (!pci_bus_is_root(bus)) { @@ -1894,9 +1896,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } =20 scope =3D aml_scope("\\_SB"); - dev =3D aml_device("PC%.02X", bus_num); + dev =3D aml_device("PCI%d", i++); aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(domain_num))); aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); if (pci_bus_is_express(bus)) { aml_append(dev, build_q35_osc_method()); @@ -2130,35 +2133,39 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, { Object *pci_host; PCIBus *bus =3D NULL; + int index =3D 0; =20 pci_host =3D acpi_get_i386_pci_host(); - if (pci_host) { + while (pci_host) { bus =3D PCI_HOST_BRIDGE(pci_host)->bus; - } =20 - if (bus) { - Aml *scope =3D aml_scope("PCI0"); - /* Scan all PCI buses. Generate tables to support hotplug. */ - build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); + if (bus) { + Aml *scope =3D aml_scope("PCI%d", index); + /* Scan all PCI buses. Generate tables to support hotplug.= */ + build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_= en); =20 - if (TPM_IS_TIS(tpm_find())) { - dev =3D aml_device("ISA.TPM"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"= ))); - aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); - crs =3D aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - /* - FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, - Rewrite to take IRQ from TPM device model and - fix default IRQ value there to use some unused IRQ - */ - /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); + /* Only add TPM once in pci domain 0 */ + if (index++ =3D=3D 0 && TPM_IS_TIS(tpm_find())) { + dev =3D aml_device("ISA.TPM"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0= C31"))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs =3D aml_resource_template(); + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + /* + FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, + Rewrite to take IRQ from TPM device model and + fix default IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } + + aml_append(sb_scope, scope); } =20 - aml_append(sb_scope, scope); + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), nex= t)); } } =20 --=20 2.7.4 From nobody Sat Feb 7 04:01:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1537197168003987.6124039585936; Mon, 17 Sep 2018 08:12:48 -0700 (PDT) Received: from localhost ([::1]:36050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1vCd-0007Lc-3c for importer@patchew.org; Mon, 17 Sep 2018 11:12:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1uyj-0004cs-G9 for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1uyh-0007Iu-Vd for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:21 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:45872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g1uyh-00078o-HZ for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:19 -0400 Received: by mail-pf1-x431.google.com with SMTP id i26-v6so7670891pfo.12 for ; Mon, 17 Sep 2018 07:58:11 -0700 (PDT) Received: from biggerfish-TM1701.lan (45.78.72.26.16clouds.com. [45.78.72.26]) by smtp.gmail.com with ESMTPSA id 87-v6sm21276632pfn.103.2018.09.17.07.58.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 07:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dqc8MVy0UMF5DqNsHbkogPaS5TUxGL1d13QBzAi5JEE=; b=djoO0/b/J5MItxaFH3qYp/z9iOzMePl6RB2M+4wGZ5lf8e4SAPZK/pSe9YcfT/ThHD JgfbdU2nWadCfb76vcjKocK4I3/mfYhhW+tNlnw2jmqbhObfsmU92VRUOVriqxfhpDfb wgR9kGm9Y1/MOnWwZIKUwxgue55eCVXSfCRqzC6KLOWVvBxGH+vyubyXzy1qP7FoYUX4 u0F+hhYUr4gdmXkajW4o8zjIdNn/VoSTDBc2xQLfpRWWR6wuTwGYg7OkesyS0DNUbyZp Tu3yQy/MtEH+HnUij2m/8UxlpCSt6oENM8McRE5xEJmhdFXVeOgvEcNRZ6kFPVT6DuKO KdbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dqc8MVy0UMF5DqNsHbkogPaS5TUxGL1d13QBzAi5JEE=; b=qEQvHBgrXMtWOq2UKL6XNyCI+9dfSPTCAGuZr+hxgXn36Dbfv+snWjX+QHWYxcH12w juFhN9trSJwQxz14BK8kQLmHCGkcpFhxzyt9txVNYe8QUPQ9FTY/NCtwUj2tEK+w3fxm 94Pm2ZfFSaBS9WqBkXvGfCLisIWrj3FLBsRIYG7K0WgoBjmE3aAgWWOlKbYwFDG6WRme JYo4FRQxYkhGGt+Wx5CTjH8Q6pq29+v1iOG+JwgIDupx4MbTg0oWGJ5acOFw4d65tSiT sGNfMGokTueRuRGKax31bFMhClFA/NotROVf0Uhtl6AfJqV2P8R/3IOw9IJ2jgYNAOJw L6Lg== X-Gm-Message-State: APzg51D4tPesUG5+r+BpihiW5EsDTirLeJpr066gdcehQawzitsaIk7G AURq79hJnJolrFwJ2EwrA2B5l5aLpS0= X-Google-Smtp-Source: ANB0VdbLscDRFD1Sl+yRyQenrYzWJDrtGp4vzSFw9J0QBXHIVgCJlC4GVL8GPqgeWEH1C/sjmy1bBQ== X-Received: by 2002:a63:9f19:: with SMTP id g25-v6mr24449597pge.39.1537196290583; Mon, 17 Sep 2018 07:58:10 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 22:57:36 +0800 Message-Id: <1537196258-12581-6-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [RFC v5 5/6] pci_expander_bridge: add config_write callback for pxb-pcie X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows SeaBIOS to configure MCFG base during initialization. The mcfg size is calculated using based on desired bus number Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 37 +++++++++++++++++++++++++= ++++ include/hw/pci-bridge/pci_expander_bridge.h | 7 ++++++ 2 files changed, 44 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 1e1999d..09413df 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -20,6 +20,7 @@ #include "hw/pci-bridge/pci_expander_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" +#include "qemu/units.h" #include "sysemu/numa.h" #include "qapi/visitor.h" =20 @@ -395,6 +396,41 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev) pxb_dev_list =3D g_list_remove(pxb_dev_list, pxb); } =20 +static void pxb_pcie_update_pciexbar(PXBDev *pxb) +{ + PCIDevice *pci_dev =3D PCI_DEVICE(pxb); + PCIBus *pxb_bus =3D pci_get_bus(pci_dev); + BusState *bus =3D BUS(QLIST_FIRST(&pxb_bus->child)); + PCIExpressHost *pehb =3D PCIE_HOST_BRIDGE(bus->parent); + + uint64_t addr; + uint32_t length; + int enable; + + addr =3D pci_get_quad(pci_dev->config + PXB_PCIE_HOST_BRIDGE_MCFG_BAR); + enable =3D addr & PXB_PCIE_HOST_BRIDGE_ENABLE; + addr &=3D PXB_PCIE_HOST_BRIDGE_PCIEXBAR_ADMSK; + length =3D (pxb->max_bus - pxb->bus_nr + 1) * MiB; + + pcie_host_mmcfg_update(pehb, enable, addr, length); +} + +static void pxb_pcie_config_write(PCIDevice *d, uint32_t address, + uint32_t val, int len) +{ + PXBDev *pxb =3D PXB_PCIE_DEV(d); + + pci_default_write_config(d, address, val, len); + + /* Since desired bus number is provided by pxb-pcie, + we just need seabios to decide the mcfg_base for us. + mcfg_size can be calculated easily */ + if (ranges_overlap(address, len, PXB_PCIE_HOST_BRIDGE_MCFG_BAR, + PXB_PCIE_HOST_BRIDGE_MCFG_BAR_SIZE)) { + pxb_pcie_update_pciexbar(pxb); + } +} + static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), @@ -459,6 +495,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass,= void *data) k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PXB_PCIE; k->class_id =3D PCI_CLASS_BRIDGE_HOST; + k->config_write =3D pxb_pcie_config_write; =20 dc->desc =3D "PCI Express Expander Bridge"; dc->props =3D pxb_pcie_dev_properties; diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index e017c62..5be0a8e 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -2,6 +2,7 @@ #define HW_PCI_EXPANDER_H =20 #include "hw/pci/pcie_host.h" +#include "hw/pci-host/q35.h" =20 #define TYPE_PXB_PCIE_HOST "pxb-pcie-host" #define PXB_PCIE_HOST_DEVICE(obj) \ @@ -13,4 +14,10 @@ typedef struct PXBPCIEHost { /*< public >*/ } PXBPCIEHost; =20 +#define PXB_PCIE_HOST_BRIDGE_MCFG_BAR 0x50 /* 64bit regis= ter */ +#define PXB_PCIE_HOST_BRIDGE_MCFG_BAR_SIZE 8 +#define PXB_PCIE_HOST_BRIDGE_ENABLE MCH_HOST_BRIDGE_PCIEXB= AREN +/* The mcfg_base of pxb-pcie is not 256MB-aligned, but MB-aligned */ +#define PXB_PCIE_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 20) + #endif --=20 2.7.4 From nobody Sat Feb 7 04:01:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1537196814993356.7398540247016; Mon, 17 Sep 2018 08:06:54 -0700 (PDT) Received: from localhost ([::1]:36015 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1v6z-0002Jo-Ed for importer@patchew.org; Mon, 17 Sep 2018 11:06:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1uyj-0004ct-GM for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1uyh-0007I7-Pe for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:21 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:33081) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g1uyh-00079b-D2 for qemu-devel@nongnu.org; Mon, 17 Sep 2018 10:58:19 -0400 Received: by mail-pl1-x643.google.com with SMTP id b97-v6so2342895plb.0 for ; Mon, 17 Sep 2018 07:58:13 -0700 (PDT) Received: from biggerfish-TM1701.lan (45.78.72.26.16clouds.com. [45.78.72.26]) by smtp.gmail.com with ESMTPSA id 87-v6sm21276632pfn.103.2018.09.17.07.58.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 07:58:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZeC13lz0nqnG5bnqoU+U/AZssli/rf27kPb6b1xqaOQ=; b=d88h+NkiKPud87XhbEbo34dL/P0JQAu6Mhd2WZLXJS1SSViPrJj6pLUE9de/SLUcAa kYzF/MUIXybYjMHIBU6vHLi7Ss1mhBsZ9kvqdrJnHIaDdeSCFtDKmiee2yUAsz7AfOu/ 0Mh3Xn0PHSD4Nrdxc10In16XIuop5ekzNpxeKdQKxfkRTpsyw6wte220vg7sIEp6wBgo cXqM1ALlb5Xz6JcNIl8eoezYkcgfjzq6ny9WUNtP/9g2jeDB0IOnWD9No+KiLty8LIkH 7u3P8tw8LhV1YgU3bqBlpZZDGUdOCYzmyRn7aWXMJJS/s/BW5MRDbIzGhj5Mh0cc888D bI5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZeC13lz0nqnG5bnqoU+U/AZssli/rf27kPb6b1xqaOQ=; b=ctlc6waV5RVfMyXNkI5eeMUTvd6NfD27fvZZGAY9idTg+bi072fjUcL8PjxKx1/Xf7 o4tacNSiaNlR4oTOuiD7a+qMtpkJSemQp/SbFsezm6wC5BEe2Isi28OsjKTaWn7yWo/J g+m390EQvMP1HFIkCO58jF5M7mY19jXA2Gc71CXjuAqLDfnj3nyyG/i/f6I4DJ3Zh/6G aX3E2Cunl5HIW/2bdRDXEC60tR/8IFKJL69JJsCyNEGdsLB6gPYkQVXFxzUIWvR8vAWt NIkgOPd0axZ4dshSYkp+uBg1fpvHdmIfQaPswG+G6OfnVU1Oq7LZtoje156EOOkdHMiE xeTQ== X-Gm-Message-State: APzg51Aamz8CLeU70k7ZYOkbTBKSZigyEdzK+h/F44i9eZRJQ7zi0yLo Qyh1zWg0gk+k1KN38kqqb/IrTtpAUiQ= X-Google-Smtp-Source: ANB0VdZdNFsA5rxFU/jbGGUjdFmI5ZLUMpcsGd3ZSLgZbg5yzRsKzbirx03Rb3lzpRYUuzXgj6kWSg== X-Received: by 2002:a17:902:2e01:: with SMTP id q1-v6mr25466356plb.40.1537196292780; Mon, 17 Sep 2018 07:58:12 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 22:57:37 +0800 Message-Id: <1537196258-12581-7-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196258-12581-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [RFC v5 6/6] pci_expander_bridge: inform seabios of desired mcfg size via hidden bar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pxb-pcie may only consumes a subset of 256 busses in a pci domain, but seab= ios does not know it unless pxb-pcies passes it to seabios. This patch places desired mcfg size into a hidden pci bar. The size is calculated based on desired bus number of a pxb-pcie Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 5 +++++ include/hw/pci-bridge/pci_expander_bridge.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 09413df..661de7c 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -370,6 +370,11 @@ static void pxb_dev_realize_common(PCIDevice *dev, boo= l pcie, Error **errp) PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST); =20 + if (pcie && pxb->domain_nr > 0) { + pci_set_long(dev->config + PXB_PCIE_HOST_BRIDGE_MCFG_SIZE, + (pxb->max_bus - pxb->bus_nr + 1) * MiB); + } + pxb_dev_list =3D g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare); return; =20 diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index 5be0a8e..9103eaa 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -20,4 +20,6 @@ typedef struct PXBPCIEHost { /* The mcfg_base of pxb-pcie is not 256MB-aligned, but MB-aligned */ #define PXB_PCIE_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 20) =20 +#define PXB_PCIE_HOST_BRIDGE_MCFG_SIZE 0x58 /* 32bit regis= ter */ + #endif --=20 2.7.4