From nobody Wed Nov 5 18:35:55 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535893958923511.7982319577901; Sun, 2 Sep 2018 06:12:38 -0700 (PDT) Received: from localhost ([::1]:40665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fwSB9-0008Js-Ce for importer@patchew.org; Sun, 02 Sep 2018 09:12:35 -0400 Received: from [2001:4830:134:3::10] (port=56117 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fwS9X-0007gL-19 for qemu-devel@nongnu.org; Sun, 02 Sep 2018 09:11:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fwRsa-0007ms-3B for qemu-devel@nongnu.org; Sun, 02 Sep 2018 08:54:04 -0400 Received: from mga02.intel.com ([134.134.136.20]:47333) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fwRow-0006qp-Qc for qemu-devel@nongnu.org; Sun, 02 Sep 2018 08:53:24 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Sep 2018 04:46:13 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by FMSMGA003.fm.intel.com with ESMTP; 02 Sep 2018 04:46:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,320,1531810800"; d="scan'208";a="77390787" From: Robert Hoo To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Sun, 2 Sep 2018 19:46:05 +0800 Message-Id: <1535888767-154680-2-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1535888767-154680-1-git-send-email-robert.hu@linux.intel.com> References: <1535888767-154680-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v4 1/3] x86: Data structure changes to support MSR based features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, qemu-devel@nongnu.org, Robert Hoo Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add FeatureWordType indicator in struct FeatureWordInfo. Change feature_word_info[] accordingly. Change existing functions that refer to feature_word_info[] accordingly. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 172 +++++++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 120 insertions(+), 52 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f24295e..a252c26 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -770,17 +770,36 @@ static void x86_cpu_vendor_words2str(char *dst, uint3= 2_t vendor1, /* missing: CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ =20 +typedef enum FeatureWordType { + CPUID_FEATURE_WORD, + MSR_FEATURE_WORD, +} FeatureWordType; + typedef struct FeatureWordInfo { - /* feature flags names are taken from "Intel Processor Identification = and + FeatureWordType type; + /* feature flags names are taken from "Intel Processor Identification a= nd * the CPUID Instruction" and AMD's "CPUID Specification". * In cases of disagreement between feature naming conventions, * aliases may be added. */ const char *feat_names[32]; - uint32_t cpuid_eax; /* Input EAX for CPUID */ - bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */ - uint32_t cpuid_ecx; /* Input ECX value for CPUID */ - int cpuid_reg; /* output register (R_* constant) */ + union { + /* If type=3D=3DCPUID_FEATURE_WORD */ + struct { + uint32_t eax; /* Input EAX for CPUID */ + bool needs_ecx; /* CPUID instruction uses ECX as input */ + uint32_t ecx; /* Input ECX value for CPUID */ + int reg; /* output register (R_* constant) */ + } cpuid; + /* If type=3D=3DMSR_FEATURE_WORD */ + struct { + uint32_t index; + struct { /*CPUID that enumerate this MSR*/ + FeatureWord cpuid_class; + uint32_t cpuid_flag; + } cpuid_dep; + } msr; + }; uint32_t tcg_features; /* Feature flags supported by TCG */ uint32_t unmigratable_flags; /* Feature flags known to be unmigratable= */ uint32_t migratable_flags; /* Feature flags known to be migratable */ @@ -790,6 +809,7 @@ typedef struct FeatureWordInfo { =20 static FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { [FEAT_1_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", @@ -800,10 +820,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "fxsr", "sse", "sse2", "ss", "ht" /* Intel htt */, "tm", "ia64", "pbe", }, - .cpuid_eax =3D 1, .cpuid_reg =3D R_EDX, + .cpuid =3D {.eax =3D 1, .reg =3D R_EDX, }, .tcg_features =3D TCG_FEATURES, }, [FEAT_1_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", "ds-cpl", "vmx", "smx", "est", @@ -814,7 +835,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { "tsc-deadline", "aes", "xsave", NULL /* osxsave */, "avx", "f16c", "rdrand", "hypervisor", }, - .cpuid_eax =3D 1, .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 1, .reg =3D R_ECX, }, .tcg_features =3D TCG_EXT_FEATURES, }, /* Feature names that are already defined on feature_name[] but @@ -823,6 +844,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. */ [FEAT_8000_0001_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, @@ -833,10 +855,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow", }, - .cpuid_eax =3D 0x80000001, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x80000001, .reg =3D R_EDX, }, .tcg_features =3D TCG_EXT2_FEATURES, }, [FEAT_8000_0001_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "lahf-lm", "cmp-legacy", "svm", "extapic", "cr8legacy", "abm", "sse4a", "misalignsse", @@ -847,7 +870,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { "perfctr-nb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000001, .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 0x80000001, .reg =3D R_ECX, }, .tcg_features =3D TCG_EXT3_FEATURES, /* * TOPOEXT is always allowed but can't be enabled blindly by @@ -857,6 +880,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { .no_autoenable_flags =3D CPUID_EXT3_TOPOEXT, }, [FEAT_C000_0001_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "xstore", "xstore-en", NULL, NULL, "xcrypt", "xcrypt-en", @@ -867,10 +891,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0xC0000001, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0xC0000001, .reg =3D R_EDX, }, .tcg_features =3D TCG_EXT4_FEATURES, }, [FEAT_KVM] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", @@ -881,10 +906,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "kvmclock-stable-bit", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D KVM_CPUID_FEATURES, .reg =3D R_EAX, }, .tcg_features =3D TCG_KVM_FEATURES, }, [FEAT_KVM_HINTS] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "kvm-hint-dedicated", NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -895,7 +921,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D KVM_CPUID_FEATURES, .reg =3D R_EDX, }, .tcg_features =3D TCG_KVM_FEATURES, /* * KVM hints aren't auto-enabled by -cpu host, they need to be @@ -904,6 +930,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { .no_autoenable_flags =3D ~0U, }, [FEAT_HYPERV_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refco= unt_access */, NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access *= /, @@ -918,9 +945,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EAX, }, }, [FEAT_HYPERV_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_create_partitions */, NULL /* hv_access_partition_i= d */, NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_bu= ffers */, @@ -934,9 +962,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EBX, }, }, [FEAT_HYPERV_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_mwait */, NULL /* hv_guest_debugging */, NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, @@ -949,9 +978,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EDX, }, }, [FEAT_SVM] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "npt", "lbrv", "svm-lock", "nrip-save", "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", @@ -962,10 +992,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x8000000A, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x8000000A, .reg =3D R_EDX, }, .tcg_features =3D TCG_SVM_FEATURES, }, [FEAT_7_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "fsgsbase", "tsc-adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", @@ -976,12 +1007,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { "clwb", "intel-pt", "avx512pf", "avx512er", "avx512cd", "sha-ni", "avx512bw", "avx512vl", }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, }, .tcg_features =3D TCG_7_0_EBX_FEATURES, }, [FEAT_7_0_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", NULL /* ospke */, NULL, "avx512vbmi2", NULL, @@ -992,12 +1024,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { NULL, "cldemote", NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_ECX, }, .tcg_features =3D TCG_7_0_ECX_FEATURES, }, [FEAT_7_0_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, @@ -1008,13 +1041,14 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, "spec-ctrl", NULL, NULL, "arch-capabilities", NULL, "ssbd", }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EDX, }, .tcg_features =3D TCG_7_0_EDX_FEATURES, .unmigratable_flags =3D CPUID_7_0_EDX_ARCH_CAPABILITIES, }, [FEAT_8000_0007_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1025,12 +1059,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000007, - .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x80000007, .reg =3D R_EDX, }, .tcg_features =3D TCG_APM_FEATURES, .unmigratable_flags =3D CPUID_APM_INVTSC, }, [FEAT_8000_0008_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1041,12 +1075,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000008, - .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 0x80000008, .reg =3D R_EBX, }, .tcg_features =3D 0, .unmigratable_flags =3D 0, }, [FEAT_XSAVE] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", NULL, NULL, NULL, NULL, @@ -1057,12 +1091,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0xd, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 1, - .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 0xd, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, }, .tcg_features =3D TCG_XSAVE_FEATURES, }, [FEAT_6_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "arat", NULL, NULL, NULL, NULL, NULL, @@ -1073,13 +1108,14 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 6, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 6, .reg =3D R_EAX, }, .tcg_features =3D TCG_6_EAX_FEATURES, }, [FEAT_XSAVE_COMP_LO] =3D { - .cpuid_eax =3D 0xD, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EAX, + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { .eax =3D 0xD, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EAX, }, .tcg_features =3D ~0U, .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | @@ -1087,9 +1123,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { XSTATE_PKRU_MASK, }, [FEAT_XSAVE_COMP_HI] =3D { - .cpuid_eax =3D 0xD, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EDX, + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { .eax =3D 0xD, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EDX, }, .tcg_features =3D ~0U, }, }; @@ -2975,21 +3012,41 @@ static const TypeInfo host_x86_cpu_type_info =3D { =20 #endif =20 +static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) +{ + assert(f->type =3D=3D CPUID_FEATURE_WORD || + f->type =3D=3D MSR_FEATURE_WORD); + switch (f->type) { + case CPUID_FEATURE_WORD: + { + const char *reg =3D get_register_name_32(f->cpuid.reg); + assert(reg); + return g_strdup_printf("CPUID.%02XH:%s", + f->cpuid.eax, reg); + } + case MSR_FEATURE_WORD: + return g_strdup_printf("MSR(%02XH)", + f->msr.index); + } + + return NULL; +} + static void report_unavailable_features(FeatureWord w, uint32_t mask) { FeatureWordInfo *f =3D &feature_word_info[w]; int i; + char *feat_word_str; =20 for (i =3D 0; i < 32; ++i) { if ((1UL << i) & mask) { - const char *reg =3D get_register_name_32(f->cpuid_reg); - assert(reg); - warn_report("%s doesn't support requested feature: " - "CPUID.%02XH:%s%s%s [bit %d]", + feat_word_str =3D feature_word_description(f, i); + warn_report("%s doesn't support requested feature: %s%s%s [bit= %d]", accel_uses_host_cpuid() ? "host" : "TCG", - f->cpuid_eax, reg, + feat_word_str, f->feat_names[i] ? "." : "", f->feat_names[i] ? f->feat_names[i] : "", i); + g_free(feat_word_str); } } } @@ -3233,11 +3290,14 @@ static void x86_cpu_get_feature_words(Object *obj, = Visitor *v, =20 for (w =3D 0; w < FEATURE_WORDS; w++) { FeatureWordInfo *wi =3D &feature_word_info[w]; + if (wi->type !=3D CPUID_FEATURE_WORD) { + continue; + } X86CPUFeatureWordInfo *qwi =3D &word_infos[w]; - qwi->cpuid_input_eax =3D wi->cpuid_eax; - qwi->has_cpuid_input_ecx =3D wi->cpuid_needs_ecx; - qwi->cpuid_input_ecx =3D wi->cpuid_ecx; - qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid_reg].qapi_enum; + qwi->cpuid_input_eax =3D wi->cpuid.eax; + qwi->has_cpuid_input_ecx =3D wi->cpuid.needs_ecx; + qwi->cpuid_input_ecx =3D wi->cpuid.ecx; + qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid.reg].qapi_enum; qwi->features =3D array[w]; =20 /* List will be in reverse order, but order shouldn't matter */ @@ -3613,9 +3673,16 @@ static uint32_t x86_cpu_get_supported_feature_word(F= eatureWord w, uint32_t r; =20 if (kvm_enabled()) { - r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax, - wi->cpuid_ecx, - wi->cpuid_reg); + switch (wi->type) { + case CPUID_FEATURE_WORD: + r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); + break; + default: + r =3D 0; + break; + } } else if (hvf_enabled()) { r =3D hvf_get_supported_cpuid(wi->cpuid_eax, wi->cpuid_ecx, @@ -4680,9 +4747,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, F= eatureWord w) { CPUX86State *env =3D &cpu->env; FeatureWordInfo *fi =3D &feature_word_info[w]; - uint32_t eax =3D fi->cpuid_eax; + uint32_t eax =3D fi->cpuid.eax; uint32_t region =3D eax & 0xF0000000; =20 + assert(feature_word_info[w].type =3D=3D CPUID_FEATURE_WORD); if (!env->features[w]) { return; } --=20 1.8.3.1