From nobody Wed Nov 5 15:09:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535032199753230.38950984524865; Thu, 23 Aug 2018 06:49:59 -0700 (PDT) Received: from localhost ([::1]:36582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fspzq-0000wo-3i for importer@patchew.org; Thu, 23 Aug 2018 09:49:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fspmC-00052C-Jn for qemu-devel@nongnu.org; Thu, 23 Aug 2018 09:35:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fspm8-00009c-HV for qemu-devel@nongnu.org; Thu, 23 Aug 2018 09:35:52 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41907 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fspm7-00006I-P1 for qemu-devel@nongnu.org; Thu, 23 Aug 2018 09:35:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 560E91A415C; Thu, 23 Aug 2018 15:34:43 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1E5521A4135; Thu, 23 Aug 2018 15:34:43 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 23 Aug 2018 15:34:12 +0200 Message-Id: <1535031276-22911-23-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535031276-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1535031276-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: James Hogan Implement emulation of nanoMIPS EXTW instruction. EXTW instruction is similar to the MIPS r6 ALIGN instruction, except that it counts the other way and in bits instead of bytes. We therefore generalise gen_align() function into a new gen_align_bits() function (which counts in bits instead of bytes and optimises when bits =3D size of the word), and implement gen_align() and a new gen_ext() based on that. Since we need to know the word size to check for when the number of bits =3D=3D the word size, the opc argument is replaced with a wordsz argument (either 32 or 64). Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5da5dcd..4fc94c6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4870,8 +4870,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int r= d, int rs, int rt, return; } =20 -static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, - int bp) +static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, + int rt, int bits) { TCGv t0; if (rd =3D=3D 0) { @@ -4879,35 +4879,40 @@ static void gen_align(DisasContext *ctx, int opc, i= nt rd, int rs, int rt, return; } t0 =3D tcg_temp_new(); - gen_load_gpr(t0, rt); - if (bp =3D=3D 0) { - switch (opc) { - case OPC_ALIGN: + if (bits =3D=3D 0 || bits =3D=3D wordsz) { + if (bits =3D=3D 0) { + gen_load_gpr(t0, rt); + } else { + gen_load_gpr(t0, rs); + } + switch (wordsz) { + case 32: tcg_gen_ext32s_tl(cpu_gpr[rd], t0); break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: + case 64: tcg_gen_mov_tl(cpu_gpr[rd], t0); break; #endif } } else { TCGv t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); - switch (opc) { - case OPC_ALIGN: + switch (wordsz) { + case 32: { TCGv_i64 t2 =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t2, t1, t0); - tcg_gen_shri_i64(t2, t2, 8 * (4 - bp)); + tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: - tcg_gen_shli_tl(t0, t0, 8 * bp); - tcg_gen_shri_tl(t1, t1, 8 * (8 - bp)); + case 64: + tcg_gen_shli_tl(t0, t0, bits); + tcg_gen_shri_tl(t1, t1, 64 - bits); tcg_gen_or_tl(cpu_gpr[rd], t1, t0); break; #endif @@ -4918,6 +4923,18 @@ static void gen_align(DisasContext *ctx, int opc, in= t rd, int rs, int rt, tcg_temp_free(t0); } =20 +static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int r= t, + int bp) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); +} + +static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt, + int shift) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift); +} + static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) { TCGv t0; @@ -14410,8 +14427,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case ALIGN: check_insn(ctx, ISA_MIPS32R6); - gen_align(ctx, OPC_ALIGN, rd, rs, rt, - extract32(ctx->opcode, 9, 2)); + gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); @@ -17618,6 +17634,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_lsa(ctx, OPC_LSA, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1); break; + case NM_EXTW: + gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); + break; case NM_POOL32AXF: gen_pool32axf_nanomips_insn(env, ctx); break; @@ -20465,7 +20484,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) switch (op2) { case OPC_ALIGN: case OPC_ALIGN_END: - gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3); + gen_align(ctx, 32, rd, rs, rt, sa & 3); break; case OPC_BITSWAP: gen_bitswap(ctx, op2, rd, rt); @@ -20491,7 +20510,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) switch (op2) { case OPC_DALIGN: case OPC_DALIGN_END: - gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7); + gen_align(ctx, 64, rd, rs, rt, sa & 7); break; case OPC_DBITSWAP: gen_bitswap(ctx, op2, rd, rt); --=20 2.7.4