From nobody Wed Nov 5 15:01:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534857773455988.2097451136029; Tue, 21 Aug 2018 06:22:53 -0700 (PDT) Received: from localhost ([::1]:53518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6cQ-0006Yo-W3 for importer@patchew.org; Tue, 21 Aug 2018 09:22:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53568) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6Nt-0001B9-C5 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:07:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6Nn-0008QX-Cl for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:07:45 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:35479 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6Nm-0008NE-QW for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:07:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3DE8E1A467F; Tue, 21 Aug 2018 15:07:35 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DB2891A4673; Tue, 21 Aug 2018 15:07:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 15:07:07 +0200 Message-Id: <1534856848-12102-26-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534856848-12102-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534856848-12102-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson Reviewed-by: Aleksandar Markovic Signed-off-by: Dimitrije Nikolic Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/cpu_loop.c | 25 +++++++++++--- target/mips/cpu.h | 2 ++ target/mips/translate.c | 86 ++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 108 insertions(+), 5 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 084ad6a..1d3dc9e 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env) target_ulong addr; target_ulong page_addr; target_ulong val; + uint32_t val_wp =3D 0; + uint32_t llnewval_wp =3D 0; int flags; int segv =3D 0; int reg; int d; + int wp; =20 addr =3D env->lladdr; page_addr =3D addr & TARGET_PAGE_MASK; @@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env) } else { reg =3D env->llreg & 0x1f; d =3D (env->llreg & 0x20) !=3D 0; - if (d) { - segv =3D get_user_s64(val, addr); + wp =3D (env->llreg & 0x40) !=3D 0; + if (!wp) { + if (d) { + segv =3D get_user_s64(val, addr); + } else { + segv =3D get_user_s32(val, addr); + } } else { segv =3D get_user_s32(val, addr); + segv |=3D get_user_s32(val_wp, addr); + llnewval_wp =3D env->llnewval_wp; } if (!segv) { - if (val !=3D env->llval) { + if (val !=3D env->llval && val_wp =3D=3D llnewval_wp) { env->active_tc.gpr[reg] =3D 0; } else { - if (d) { - segv =3D put_user_u64(env->llnewval, addr); + if (!wp) { + if (d) { + segv =3D put_user_u64(env->llnewval, addr); + } else { + segv =3D put_user_u32(env->llnewval, addr); + } } else { segv =3D put_user_u32(env->llnewval, addr); + segv |=3D put_user_u32(env->llnewval_wp, addr + 4); } if (!segv) { env->active_tc.gpr[reg] =3D 1; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202c..28af4d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -506,6 +506,8 @@ struct CPUMIPSState { uint64_t lladdr; target_ulong llval; target_ulong llnewval; + uint64_t llval_wp; + uint32_t llnewval_wp; target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; diff --git a/target/mips/translate.c b/target/mips/translate.c index dc1760b..ebe56d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1916,6 +1916,18 @@ static inline void check_mvh(DisasContext *ctx) } #endif =20 +/* + * This code generates a "reserved instruction" exception if the + * Config5 XNP bit is set. + */ +static inline void check_xnp(DisasContext *ctx) +{ + if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { + generate_exception_end(ctx, EXCP_RI); + } +} + + /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing all callers for gen_load_fpr32 when we need the CTX parameter for @@ -2362,6 +2374,31 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } =20 +static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ + TCGv taddr =3D tcg_temp_new(); + TCGv_i64 tval =3D tcg_temp_new_i64(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_extr_i64_tl(tmp2, tmp1, tval); +#else + tcg_gen_extr_i64_tl(tmp1, tmp2, tval); +#endif + gen_store_gpr(tmp1, reg1); + tcg_temp_free(tmp1); + gen_store_gpr(tmp2, reg2); + tcg_temp_free(tmp2); + tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_temp_free_i64(tval); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_temp_free(taddr); +} + /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, int base, int offset) @@ -2458,6 +2495,51 @@ static void gen_st_cond (DisasContext *ctx, uint32_t= opc, int rt, tcg_temp_free(t0); } =20 +static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ + TCGv taddr =3D tcg_temp_local_new(); + TCGv lladdr =3D tcg_temp_local_new(); + TCGv_i64 tval =3D tcg_temp_new_i64(); + TCGv_i64 llval =3D tcg_temp_new_i64(); + TCGv_i64 val =3D tcg_temp_new_i64(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + TCGLabel *lab_fail =3D gen_new_label(); + TCGLabel *lab_done =3D gen_new_label(); + + gen_base_offset_addr(ctx, taddr, base, offset); + + tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail); + + gen_load_gpr(tmp1, reg1); + gen_load_gpr(tmp2, reg2); + +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_concat_tl_i64(tval, tmp2, tmp1); +#else + tcg_gen_concat_tl_i64(tval, tmp1, tmp2); +#endif + + tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, + ctx->mem_idx, MO_64); + if (reg1 !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[reg1], 1); + } + tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done); + + gen_set_label(lab_fail); + + if (reg1 !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[reg1], 0); + } + gen_set_label(lab_done); + tcg_gen_movi_tl(lladdr, -1); + tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); +} + /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, TCGv t0) @@ -18118,6 +18200,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_ld(ctx, OPC_LL, rt, rs, s); break; case NM_LLWP: + check_xnp(ctx); + gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); break; } break; @@ -18127,6 +18211,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st_cond(ctx, OPC_SC, rt, rs, s); break; case NM_SCWP: + check_xnp(ctx); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); break; } break; --=20 2.7.4