From nobody Sat Feb 7 06:07:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534821474755753.0508024796842; Mon, 20 Aug 2018 20:17:54 -0700 (PDT) Received: from localhost ([::1]:50444 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frxB3-0008F4-Jf for importer@patchew.org; Mon, 20 Aug 2018 23:17:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59030) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frx91-0007E0-Mu for qemu-devel@nongnu.org; Mon, 20 Aug 2018 23:15:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1frx90-0002NM-UX for qemu-devel@nongnu.org; Mon, 20 Aug 2018 23:15:47 -0400 Received: from mga14.intel.com ([192.55.52.115]:48601) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1frx90-0002Kt-Ma for qemu-devel@nongnu.org; Mon, 20 Aug 2018 23:15:46 -0400 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2018 20:15:46 -0700 Received: from unknown (HELO liujing-dell.bj.intel.com) ([10.238.145.49]) by orsmga008.jf.intel.com with ESMTP; 20 Aug 2018 20:15:44 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,267,1531810800"; d="scan'208";a="66818015" From: Jing Liu To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 11:18:07 +0800 Message-Id: <1534821487-14189-3-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534821487-14189-1-git-send-email-jing2.liu@linux.intel.com> References: <1534821487-14189-1-git-send-email-jing2.liu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH v3 2/2] hw/pci: add PCI resource reserve capability to legacy PCI bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, Jing Liu , anthony.xu@intel.com, pbonzini@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add hint to firmware (e.g. SeaBIOS) to reserve addtional BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the resource reserve capability deleting in pci_bridge_dev_exitfn. Signed-off-by: Jing Liu Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/pci_bridge_dev.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index b2d861d..97a8e8b 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -46,6 +46,9 @@ struct PCIBridgeDev { uint32_t flags; =20 OnOffAuto msi; + + /* additional resources to reserve */ + PCIResReserve res_reserve; }; typedef struct PCIBridgeDev PCIBridgeDev; =20 @@ -95,6 +98,12 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error= **errp) error_free(local_err); } =20 + err =3D pci_bridge_qemu_reserve_cap_init(dev, 0, + bridge_dev->res_reserve, errp); + if (err) { + goto cap_error; + } + if (shpc_present(dev)) { /* TODO: spec recommends using 64 bit prefetcheable BAR. * Check whether that works well. */ @@ -103,6 +112,8 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Erro= r **errp) } return; =20 +cap_error: + msi_uninit(dev); msi_error: slotid_cap_cleanup(dev); slotid_error: @@ -116,6 +127,8 @@ shpc_error: static void pci_bridge_dev_exitfn(PCIDevice *dev) { PCIBridgeDev *bridge_dev =3D PCI_BRIDGE_DEV(dev); + + pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap)); if (msi_present(dev)) { msi_uninit(dev); } @@ -162,6 +175,17 @@ static Property pci_bridge_dev_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_SHPC_REQ, true), + DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev, + res_reserve.bus, -1), + DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev, + res_reserve.io, -1), + DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev, + res_reserve.mem_non_pref, -1), + DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev, + res_reserve.mem_pref_32, -1), + DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev, + res_reserve.mem_pref_64, -1), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 1.8.3.1