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X-Received-From: 2607:f8b0:4003:c06::242 Subject: [Qemu-devel] [PATCH v2 08/10] i2c:pm_smbus: Add the ability to force block transfer enable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Corey Minyard The PIIX4 hardware has block transfer buffer always enabled in the hardware, but the i801 does not. Add a parameter to pm_smbus_init to force on the block transfer so the PIIX4 handler can enable this by default, as it was disabled by default before. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/acpi/piix4.c | 2 +- hw/i2c/pm_smbus.c | 5 ++++- hw/i2c/smbus_ich9.c | 2 +- hw/isa/vt82c686.c | 2 +- include/hw/i2c/pm_smbus.h | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index f8d8d2e..313305f 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -513,7 +513,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **er= rp) pci_conf[0x90] =3D s->smb_io_base | 1; pci_conf[0x91] =3D s->smb_io_base >> 8; pci_conf[0xd2] =3D 0x09; - pm_smbus_init(DEVICE(dev), &s->smb); + pm_smbus_init(DEVICE(dev), &s->smb, true); memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base, &s->smb.io); diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 10ba208..4d021bb 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -422,11 +422,14 @@ const VMStateDescription pmsmb_vmstate =3D { } }; =20 -void pm_smbus_init(DeviceState *parent, PMSMBus *smb) +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk) { smb->op_done =3D true; smb->reset =3D pm_smbus_reset; smb->smbus =3D i2c_init_bus(parent, "i2c"); + if (force_aux_blk) { + smb->smb_auxctl |=3D AUX_BLK; + } memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, "pm-smbus", 64); } diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 316c2a4..5860fc9 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -88,7 +88,7 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp) pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); /* TODO bar0, bar1: 64bit BAR support*/ =20 - pm_smbus_init(&d->qdev, &s->smb); + pm_smbus_init(&d->qdev, &s->smb, false); pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO, &s->smb.io); } diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index cff1946..7302f6d 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -370,7 +370,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error = **errp) pci_conf[0x90] =3D s->smb_io_base | 1; pci_conf[0x91] =3D s->smb_io_base >> 8; pci_conf[0xd2] =3D 0x90; - pm_smbus_init(&s->dev.qdev, &s->smb); + pm_smbus_init(&s->dev.qdev, &s->smb, false); memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.i= o); =20 apm_init(dev, &s->apm, NULL, s); diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index cfe596f..471345e 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -33,7 +33,7 @@ typedef struct PMSMBus { bool op_done; } PMSMBus; =20 -void pm_smbus_init(DeviceState *parent, PMSMBus *smb); +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk); =20 extern const VMStateDescription pmsmb_vmstate; =20 --=20 2.7.4