From nobody Wed Nov 5 13:13:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534432303510460.33550930851106; Thu, 16 Aug 2018 08:11:43 -0700 (PDT) Received: from localhost ([::1]:56254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJw6-0001mJ-1l for importer@patchew.org; Thu, 16 Aug 2018 11:11:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56068) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJl3-0005Nn-Sr for qemu-devel@nongnu.org; Thu, 16 Aug 2018 11:00:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqJkv-0000hN-BN for qemu-devel@nongnu.org; Thu, 16 Aug 2018 11:00:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:43527 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqJku-0000e5-KE for qemu-devel@nongnu.org; Thu, 16 Aug 2018 11:00:09 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D92721A23ED; Thu, 16 Aug 2018 16:59:00 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id B18DF1A23EC; Thu, 16 Aug 2018 16:59:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 16:57:33 +0200 Message-Id: <1534431497-1385-41-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. This is done by adding a field in hflags for MT bit, and adding functions check_mt() and check_cp0_mt(). Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/cpu.h | 3 ++- target/mips/internal.h | 6 +++++- target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++-------- 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 468b686..bf9c634 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -556,7 +556,7 @@ struct CPUMIPSState { #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x3F5807FF +#define MIPS_HFLAG_TMASK 0x7F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -608,6 +608,7 @@ struct CPUMIPSState { #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC ta= g */ #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ #define MIPS_HFLAG_XNP 0x20000000 +#define MIPS_HFLAG_MT 0x40000000 target_ulong btarget; /* Jump / branch target */ target_ulong bcond; /* Branch condition (if needed) */ =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index 97485da..c0e447b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,8 @@ static inline void compute_hflags(CPUMIPSState *env) MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | - MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP); + MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP | + MIPS_HFLAG_MT); if (env->CP0_Status & (1 << CP0St_ERL)) { env->hflags |=3D MIPS_HFLAG_ERL; } @@ -405,6 +406,9 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->CP0_Config5 & (1 << CP0C5_XNP)) { env->hflags |=3D MIPS_HFLAG_XNP; } + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + env->hflags |=3D MIPS_HFLAG_MT; + } } =20 void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/translate.c b/target/mips/translate.c index dcb3d25..e8c0509 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1925,6 +1925,35 @@ static inline void check_xnp(DisasContext *ctx) } } =20 +/* + * This code generates a "reserved instruction" exception if the + * Config5 MT bit is NOT set. + */ +static inline void check_mt(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MT))) { + generate_exception_end(ctx, EXCP_RI); + } +} + +/* + * This code generates a "coprocessor unusable" exception if CP0 is not + * available, and, if that is not the case, generates a "reserved instruct= ion" + * exception if the Config5 MT bit is NOT set. This is needed for availabi= lity + * control of some of MT ASE instructions. + */ +static inline void check_cp0_mt(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { + generate_exception_err(ctx, EXCP_CpU, 0); + } else { + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MT))) { + generate_exception_err(ctx, EXCP_RI, 0); + } + } +} + + =20 /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing @@ -8471,7 +8500,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, opn =3D "mthc0"; break; case OPC_MFTR: - check_insn(ctx, ASE_MT); + check_cp0_enabled(ctx); if (rd =3D=3D 0) { /* Treat as NOP. */ return; @@ -8481,7 +8510,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, opn =3D "mftr"; break; case OPC_MTTR: - check_insn(ctx, ASE_MT); + check_cp0_enabled(ctx); gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); opn =3D "mttr"; @@ -21797,7 +21826,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); break; case OPC_FORK: - check_insn(ctx, ASE_MT); + check_mt(ctx); { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -21810,7 +21839,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) } break; case OPC_YIELD: - check_insn(ctx, ASE_MT); + check_mt(ctx); { TCGv t0 =3D tcg_temp_new(); =20 @@ -23107,22 +23136,22 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) op2 =3D MASK_MFMC0(ctx->opcode); switch (op2) { case OPC_DMT: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_dmt(t0); gen_store_gpr(t0, rt); break; case OPC_EMT: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_emt(t0); gen_store_gpr(t0, rt); break; case OPC_DVPE: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_EVPE: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); break; --=20 2.7.4