From nobody Wed Nov 5 13:13:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534431966763464.5808489308771; Thu, 16 Aug 2018 08:06:06 -0700 (PDT) Received: from localhost ([::1]:56225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJqf-0004zg-K5 for importer@patchew.org; Thu, 16 Aug 2018 11:06:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55728) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJks-0005Fg-Gi for qemu-devel@nongnu.org; Thu, 16 Aug 2018 11:00:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqJkg-0000Vw-MX for qemu-devel@nongnu.org; Thu, 16 Aug 2018 11:00:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:40309 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqJkg-0000UP-7N for qemu-devel@nongnu.org; Thu, 16 Aug 2018 10:59:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CD8EA1A23B4; Thu, 16 Aug 2018 16:58:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A473B1A23B5; Thu, 16 Aug 2018 16:58:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 16:57:03 +0200 Message-Id: <1534431497-1385-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v9 10/84] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 395368b..bdd880b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4897,12 +4897,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, = int reg, int sel) { const char *rn =3D "invalid"; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn =3D "EntryLo0"; break; @@ -4913,6 +4912,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn =3D "EntryLo1"; break; @@ -4965,12 +4965,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, = int reg, int sel) const char *rn =3D "invalid"; uint64_t mask =3D ctx->PAMask >> 36; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn =3D "EntryLo0"; @@ -4982,6 +4981,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn =3D "EntryLo1"; --=20 2.7.4