From nobody Wed Nov 5 10:34:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534411639539543.1790029643206; Thu, 16 Aug 2018 02:27:19 -0700 (PDT) Received: from localhost ([::1]:54535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEYk-0005lA-3E for importer@patchew.org; Thu, 16 Aug 2018 05:27:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEWr-0004HL-Bt for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqEWn-00079Y-QN for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:17 -0400 Received: from mga07.intel.com ([134.134.136.100]:21412) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqEWn-00077o-GU for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:13 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2018 02:25:12 -0700 Received: from unknown (HELO liujing-dell.bj.intel.com) ([10.238.145.49]) by fmsmga002.fm.intel.com with ESMTP; 16 Aug 2018 02:25:10 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,246,1531810800"; d="scan'208";a="77268934" From: Jing Liu To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 17:28:14 +0800 Message-Id: <1534411696-6454-2-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> References: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 Subject: [Qemu-devel] [PATCH v2 1/3] hw/pci: factor PCI reserve resources to a separate structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, Jing Liu , anthony.xu@intel.com, pbonzini@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve" and "pref64_reserve" fields of the "GenPCIERootPort" structure out to "PCIResReserve" structure, so that other PCI bridges can reuse it to add resource reserve capability. Signed-off-by: Jing Liu --- hw/pci-bridge/gen_pcie_root_port.c | 32 ++++++++++++++++---------------- hw/pci/pci_bridge.c | 38 +++++++++++++++++-----------------= ---- include/hw/pci/pci_bridge.h | 17 ++++++++++++----- 3 files changed, 45 insertions(+), 42 deletions(-) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index d117e20..babce3c 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -29,12 +29,7 @@ typedef struct GenPCIERootPort { =20 bool migrate_msix; =20 - /* additional resources to reserve on firmware init */ - uint32_t bus_reserve; - uint64_t io_reserve; - uint64_t mem_reserve; - uint64_t pref32_reserve; - uint64_t pref64_reserve; + PCIResReserve res_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -82,16 +77,15 @@ static void gen_rp_realize(DeviceState *dev, Error **er= rp) return; } =20 - int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, - grp->io_reserve, grp->mem_reserve, grp->pref32_reserve, - grp->pref64_reserve, errp); + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, + grp->res_reserve, errp); =20 if (rc < 0) { rpc->parent_class.exit(d); return; } =20 - if (!grp->io_reserve) { + if (!grp->res_reserve.io_reserve) { pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, PCI_COMMAND_IO); d->wmask[PCI_IO_BASE] =3D 0; @@ -117,12 +111,18 @@ static const VMStateDescription vmstate_rp_dev =3D { }; =20 static Property gen_rp_props[] =3D { - DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), - DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), - DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1), - DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1), - DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1= ), - DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1= ), + DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, + migrate_msix, true), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, + res_reserve.bus_reserve, -1), + DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, + res_reserve.io_reserve, -1), + DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, + res_reserve.mem_reserve, -1), + DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, + res_reserve.pref32_reserve, -1), + DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, + res_reserve.pref64_reserve, -1), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 40a39f5..15b055e 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -411,38 +411,34 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bu= s_name, =20 =20 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, - uint32_t bus_reserve, uint64_t io_res= erve, - uint64_t mem_non_pref_reserve, - uint64_t mem_pref_32_reserve, - uint64_t mem_pref_64_reserve, - Error **errp) + PCIResReserve res, Error **errp) { - if (mem_pref_32_reserve !=3D (uint64_t)-1 && - mem_pref_64_reserve !=3D (uint64_t)-1) { + if (res.pref32_reserve !=3D (uint64_t)-1 && + res.pref64_reserve !=3D (uint64_t)-1) { error_setg(errp, "PCI resource reserve cap: PREF32 and PREF64 conflict"); return -EINVAL; } =20 - if (mem_non_pref_reserve !=3D (uint64_t)-1 && - mem_non_pref_reserve >=3D (1ULL << 32)) { + if (res.mem_reserve !=3D (uint64_t)-1 && + res.mem_reserve >=3D (1ULL << 32)) { error_setg(errp, "PCI resource reserve cap: mem-reserve must be less tha= n 4G"); return -EINVAL; } =20 - if (mem_pref_32_reserve !=3D (uint64_t)-1 && - mem_pref_32_reserve >=3D (1ULL << 32)) { + if (res.pref32_reserve !=3D (uint64_t)-1 && + res.pref32_reserve >=3D (1ULL << 32)) { error_setg(errp, "PCI resource reserve cap: pref32-reserve must be less= than 4G"); return -EINVAL; } =20 - if (bus_reserve =3D=3D (uint32_t)-1 && - io_reserve =3D=3D (uint64_t)-1 && - mem_non_pref_reserve =3D=3D (uint64_t)-1 && - mem_pref_32_reserve =3D=3D (uint64_t)-1 && - mem_pref_64_reserve =3D=3D (uint64_t)-1) { + if (res.bus_reserve =3D=3D (uint32_t)-1 && + res.io_reserve =3D=3D (uint64_t)-1 && + res.mem_reserve =3D=3D (uint64_t)-1 && + res.pref32_reserve =3D=3D (uint64_t)-1 && + res.pref64_reserve =3D=3D (uint64_t)-1) { return 0; } =20 @@ -450,11 +446,11 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, = int cap_offset, PCIBridgeQemuCap cap =3D { .len =3D cap_len, .type =3D REDHAT_PCI_CAP_RESOURCE_RESERVE, - .bus_res =3D bus_reserve, - .io =3D io_reserve, - .mem =3D mem_non_pref_reserve, - .mem_pref_32 =3D mem_pref_32_reserve, - .mem_pref_64 =3D mem_pref_64_reserve + .bus_res =3D res.bus_reserve, + .io =3D res.io_reserve, + .mem =3D res.mem_reserve, + .mem_pref_32 =3D res.pref32_reserve, + .mem_pref_64 =3D res.pref64_reserve }; =20 int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 0347da5..6186a32 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -133,11 +133,18 @@ typedef struct PCIBridgeQemuCap { =20 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 =20 +/* + * additional resources to reserve on firmware init + */ +typedef struct PCIResReserve { + uint32_t bus_reserve; + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref32_reserve; + uint64_t pref64_reserve; +} PCIResReserve; + int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, - uint32_t bus_reserve, uint64_t io_reserve, - uint64_t mem_non_pref_reserve, - uint64_t mem_pref_32_reserve, - uint64_t mem_pref_64_reserve, - Error **errp); + PCIResReserve res_reserve, Error **errp); =20 #endif /* QEMU_PCI_BRIDGE_H */ --=20 1.8.3.1 From nobody Wed Nov 5 10:34:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534411649348607.4154597758072; Thu, 16 Aug 2018 02:27:29 -0700 (PDT) Received: from localhost ([::1]:54536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEYy-0005w1-5h for importer@patchew.org; Thu, 16 Aug 2018 05:27:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEX2-0004ek-HG for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqEWz-0007GT-BC for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:28 -0400 Received: from mga07.intel.com ([134.134.136.100]:21421) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqEWr-0007B3-VI for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:19 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2018 02:25:17 -0700 Received: from unknown (HELO liujing-dell.bj.intel.com) ([10.238.145.49]) by fmsmga002.fm.intel.com with ESMTP; 16 Aug 2018 02:25:15 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,246,1531810800"; d="scan'208";a="77269070" From: Jing Liu To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 17:28:15 +0800 Message-Id: <1534411696-6454-3-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> References: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 Subject: [Qemu-devel] [PATCH v2 2/3] hw/pci: add teardown function for PCI resource reserve capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, Jing Liu , anthony.xu@intel.com, pbonzini@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clean up the PCI config space of resource reserve capability. Signed-off-by: Jing Liu --- hw/pci/pci_bridge.c | 9 +++++++++ include/hw/pci/pci_bridge.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 15b055e..dbcee90 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -465,6 +465,15 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, i= nt cap_offset, return 0; } =20 +void pci_bridge_qemu_reserve_cap_uninit(PCIDevice *dev) +{ + uint8_t pos =3D pci_find_capability(dev, PCI_CAP_ID_VNDR); + + pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap)); + memset(dev->config + pos + PCI_CAP_FLAGS, 0, + sizeof(PCIBridgeQemuCap) - PCI_CAP_FLAGS); +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 6186a32..b1e25ad 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -147,4 +147,5 @@ typedef struct PCIResReserve { int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, PCIResReserve res_reserve, Error **errp); =20 +void pci_bridge_qemu_reserve_cap_uninit(PCIDevice *dev); #endif /* QEMU_PCI_BRIDGE_H */ --=20 1.8.3.1 From nobody Wed Nov 5 10:34:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534411652457922.778675633725; Thu, 16 Aug 2018 02:27:32 -0700 (PDT) Received: from localhost ([::1]:54537 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEZ1-0005zN-6i for importer@patchew.org; Thu, 16 Aug 2018 05:27:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqEX2-0004em-Hz for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqEX1-0007HN-9d for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:28 -0400 Received: from mga07.intel.com ([134.134.136.100]:21438) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqEWx-0007By-4b for qemu-devel@nongnu.org; Thu, 16 Aug 2018 05:25:25 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2018 02:25:20 -0700 Received: from unknown (HELO liujing-dell.bj.intel.com) ([10.238.145.49]) by fmsmga002.fm.intel.com with ESMTP; 16 Aug 2018 02:25:18 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,246,1531810800"; d="scan'208";a="77269085" From: Jing Liu To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 17:28:16 +0800 Message-Id: <1534411696-6454-4-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> References: <1534411696-6454-1-git-send-email-jing2.liu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 Subject: [Qemu-devel] [PATCH v2 3/3] hw/pci: add PCI resource reserve capability to legacy PCI bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, Jing Liu , anthony.xu@intel.com, pbonzini@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add hint to firmware (e.g. SeaBIOS) to reserve addtional BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Signed-off-by: Jing Liu --- hw/pci-bridge/pci_bridge_dev.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index b2d861d..874e618 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -46,6 +46,8 @@ struct PCIBridgeDev { uint32_t flags; =20 OnOffAuto msi; + + PCIResReserve res_reserve; }; typedef struct PCIBridgeDev PCIBridgeDev; =20 @@ -95,6 +97,12 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error= **errp) error_free(local_err); } =20 + err =3D pci_bridge_qemu_reserve_cap_init(dev, 0, + bridge_dev->res_reserve, errp); + if (err) { + goto cap_error; + } + if (shpc_present(dev)) { /* TODO: spec recommends using 64 bit prefetcheable BAR. * Check whether that works well. */ @@ -103,6 +111,10 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Err= or **errp) } return; =20 +cap_error: + if (msi_present(dev)) { + msi_uninit(dev); + } msi_error: slotid_cap_cleanup(dev); slotid_error: @@ -116,6 +128,8 @@ shpc_error: static void pci_bridge_dev_exitfn(PCIDevice *dev) { PCIBridgeDev *bridge_dev =3D PCI_BRIDGE_DEV(dev); + + pci_bridge_qemu_reserve_cap_uninit(dev); if (msi_present(dev)) { msi_uninit(dev); } @@ -162,6 +176,17 @@ static Property pci_bridge_dev_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_SHPC_REQ, true), + DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev, + res_reserve.bus_reserve, -1), + DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev, + res_reserve.io_reserve, -1), + DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev, + res_reserve.mem_reserve, -1), + DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev, + res_reserve.pref32_reserve, -1), + DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev, + res_reserve.pref64_reserve, -1), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 1.8.3.1