From nobody Wed Nov 5 13:13:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534272324571572.9335245952191; Tue, 14 Aug 2018 11:45:24 -0700 (PDT) Received: from localhost ([::1]:45733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeJn-0000e1-Cd for importer@patchew.org; Tue, 14 Aug 2018 14:45:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdtP-0003Q6-Ux for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:19:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdss-0005v3-1C for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:07 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52243 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdsr-0005tv-9U for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:17:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5E83E1A22A1; Tue, 14 Aug 2018 20:17:08 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id ECC0D1A2210; Tue, 14 Aug 2018 20:17:07 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 20:16:50 +0200 Message-Id: <1534270621-27332-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534270621-27332-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534270621-27332-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 08/19] target/mips: Add support for availability control via bit XNP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Add a field in hflags for XNP bit, and a function check_xnp(). Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/cpu.h | 3 ++- target/mips/internal.h | 5 ++++- target/mips/translate.c | 12 ++++++++++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202c..02ea91e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -554,7 +554,7 @@ struct CPUMIPSState { #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x1F5807FF +#define MIPS_HFLAG_TMASK 0x3F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -605,6 +605,7 @@ struct CPUMIPSState { #define MIPS_HFLAG_ELPA 0x4000000 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC ta= g */ #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ +#define MIPS_HFLAG_XNP 0x20000000 target_ulong btarget; /* Jump / branch target */ target_ulong bcond; /* Branch condition (if needed) */ =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index e41051f..97485da 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | - MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); + MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP); if (env->CP0_Status & (1 << CP0St_ERL)) { env->hflags |=3D MIPS_HFLAG_ERL; } @@ -402,6 +402,9 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_ELPA; } } + if (env->CP0_Config5 & (1 << CP0C5_XNP)) { + env->hflags |=3D MIPS_HFLAG_XNP; + } } =20 void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/translate.c b/target/mips/translate.c index ae3aaab..35342e2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1902,6 +1902,18 @@ static inline void check_mvh(DisasContext *ctx) } #endif =20 +/* + * This code generates a "reserved instruction" exception if the + * Config5 XNP bit is set. + */ +static inline void check_xnp(DisasContext *ctx) +{ + if (unlikely(ctx->hflags & MIPS_HFLAG_XNP)) { + generate_exception_end(ctx, EXCP_RI); + } +} + + /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing all callers for gen_load_fpr32 when we need the CTX parameter for --=20 2.7.4