From nobody Wed Nov 5 10:09:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534183371231853.7043759424046; Mon, 13 Aug 2018 11:02:51 -0700 (PDT) Received: from localhost ([::1]:40686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpHAv-0005Q2-IG for importer@patchew.org; Mon, 13 Aug 2018 14:02:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpH34-0005Ob-6Y for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpH32-00071n-5h for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:34 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55295 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpH31-0006xJ-R0 for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:32 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 917E01A2260; Mon, 13 Aug 2018 19:54:08 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6B4DB1A2171; Mon, 13 Aug 2018 19:54:08 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 13 Aug 2018 19:52:28 +0200 Message-Id: <1534182832-554-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 03/87] target/mips: Avoid case statements formulated by ranges - part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 78 ++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 71 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 051dda5..b944ea2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -902,8 +902,21 @@ enum { OPC_MTTR =3D (0x0C << 21) | OPC_CP0, OPC_WRPGPR =3D (0x0E << 21) | OPC_CP0, OPC_C0 =3D (0x10 << 21) | OPC_CP0, - OPC_C0_FIRST =3D (0x10 << 21) | OPC_CP0, - OPC_C0_LAST =3D (0x1F << 21) | OPC_CP0, + OPC_C0_1 =3D (0x11 << 21) | OPC_CP0, + OPC_C0_2 =3D (0x12 << 21) | OPC_CP0, + OPC_C0_3 =3D (0x13 << 21) | OPC_CP0, + OPC_C0_4 =3D (0x14 << 21) | OPC_CP0, + OPC_C0_5 =3D (0x15 << 21) | OPC_CP0, + OPC_C0_6 =3D (0x16 << 21) | OPC_CP0, + OPC_C0_7 =3D (0x17 << 21) | OPC_CP0, + OPC_C0_8 =3D (0x18 << 21) | OPC_CP0, + OPC_C0_9 =3D (0x19 << 21) | OPC_CP0, + OPC_C0_A =3D (0x1A << 21) | OPC_CP0, + OPC_C0_B =3D (0x1B << 21) | OPC_CP0, + OPC_C0_C =3D (0x1C << 21) | OPC_CP0, + OPC_C0_D =3D (0x1D << 21) | OPC_CP0, + OPC_C0_E =3D (0x1E << 21) | OPC_CP0, + OPC_C0_F =3D (0x1F << 21) | OPC_CP0, }; =20 /* MFMC0 opcodes */ @@ -12490,10 +12503,22 @@ enum { /* PCREL Instructions perform PC-Relative address calculation. bits 20..16= */ enum { ADDIUPC_00 =3D 0x00, + ADDIUPC_01 =3D 0x01, + ADDIUPC_02 =3D 0x02, + ADDIUPC_03 =3D 0x03, + ADDIUPC_04 =3D 0x04, + ADDIUPC_05 =3D 0x05, + ADDIUPC_06 =3D 0x06, ADDIUPC_07 =3D 0x07, AUIPC =3D 0x1e, ALUIPC =3D 0x1f, LWPC_08 =3D 0x08, + LWPC_09 =3D 0x09, + LWPC_0A =3D 0x0A, + LWPC_0B =3D 0x0B, + LWPC_0C =3D 0x0C, + LWPC_0D =3D 0x0D, + LWPC_0E =3D 0x0E, LWPC_0F =3D 0x0F, }; =20 @@ -12928,12 +12953,16 @@ enum { R6_LWM16 =3D 0x02, R6_JRC16 =3D 0x03, MOVEP =3D 0x04, + MOVEP_05 =3D 0x05, + MOVEP_06 =3D 0x06, MOVEP_07 =3D 0x07, R6_XOR16 =3D 0x08, R6_OR16 =3D 0x09, R6_SWM16 =3D 0x0a, JALRC16 =3D 0x0b, MOVEP_0C =3D 0x0c, + MOVEP_0D =3D 0x0d, + MOVEP_0E =3D 0x0e, MOVEP_0F =3D 0x0f, JRCADDIUSP =3D 0x13, R6_BREAK16 =3D 0x1b, @@ -13251,8 +13280,14 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0); } break; - case MOVEP ... MOVEP_07: - case MOVEP_0C ... MOVEP_0F: + case MOVEP: + case MOVEP_05: + case MOVEP_06: + case MOVEP_07: + case MOVEP_0C: + case MOVEP_0D: + case MOVEP_0E: + case MOVEP_0F: { int enc_dest =3D uMIPS_RD(ctx->opcode); int enc_rt =3D uMIPS_RS2(ctx->opcode); @@ -15230,7 +15265,14 @@ static void decode_micromips32_opc(CPUMIPSState *e= nv, DisasContext *ctx) if (ctx->insn_flags & ISA_MIPS32R6) { /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { - case ADDIUPC_00 ... ADDIUPC_07: + case ADDIUPC_00: + case ADDIUPC_01: + case ADDIUPC_02: + case ADDIUPC_03: + case ADDIUPC_04: + case ADDIUPC_05: + case ADDIUPC_06: + case ADDIUPC_07: gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt); break; case AUIPC: @@ -15239,7 +15281,14 @@ static void decode_micromips32_opc(CPUMIPSState *e= nv, DisasContext *ctx) case ALUIPC: gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt); break; - case LWPC_08 ... LWPC_0F: + case LWPC_08: + case LWPC_09: + case LWPC_0A: + case LWPC_0B: + case LWPC_0C: + case LWPC_0D: + case LWPC_0E: + case LWPC_0F: gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt); break; default: @@ -19790,7 +19839,22 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) gen_cp0(env, ctx, op1, rt, rd); #endif /* !CONFIG_USER_ONLY */ break; - case OPC_C0_FIRST ... OPC_C0_LAST: + case OPC_C0: + case OPC_C0_1: + case OPC_C0_2: + case OPC_C0_3: + case OPC_C0_4: + case OPC_C0_5: + case OPC_C0_6: + case OPC_C0_7: + case OPC_C0_8: + case OPC_C0_9: + case OPC_C0_A: + case OPC_C0_B: + case OPC_C0_C: + case OPC_C0_D: + case OPC_C0_E: + case OPC_C0_F: #ifndef CONFIG_USER_ONLY gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); #endif /* !CONFIG_USER_ONLY */ --=20 2.7.4