From nobody Wed Nov 5 10:10:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534183735347444.0011248536571; Mon, 13 Aug 2018 11:08:55 -0700 (PDT) Received: from localhost ([::1]:40716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpHGs-0002bg-EJ for importer@patchew.org; Mon, 13 Aug 2018 14:08:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59344) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpH36-0005Ok-Cg for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpH32-00072V-Tq for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55743 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpH32-00071U-Ik for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:32 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0DD361A227E; Mon, 13 Aug 2018 19:54:09 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DF4701A2271; Mon, 13 Aug 2018 19:54:08 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 13 Aug 2018 19:52:35 +0200 Message-Id: <1534182832-554-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability control X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index b73f434..af9714b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8393,7 +8393,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, opn =3D "mthc0"; break; case OPC_MFTR: - check_insn(ctx, ASE_MT); + check_cp0_enabled(ctx); if (rd =3D=3D 0) { /* Treat as NOP. */ return; @@ -8403,7 +8403,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, opn =3D "mftr"; break; case OPC_MTTR: - check_insn(ctx, ASE_MT); + check_cp0_enabled(ctx); gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); opn =3D "mttr"; @@ -18619,7 +18619,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); break; case OPC_FORK: - check_insn(ctx, ASE_MT); + check_mt(ctx); { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -18632,7 +18632,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) } break; case OPC_YIELD: - check_insn(ctx, ASE_MT); + check_mt(ctx); { TCGv t0 =3D tcg_temp_new(); =20 @@ -19929,22 +19929,22 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) op2 =3D MASK_MFMC0(ctx->opcode); switch (op2) { case OPC_DMT: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_dmt(t0); gen_store_gpr(t0, rt); break; case OPC_EMT: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_emt(t0); gen_store_gpr(t0, rt); break; case OPC_DVPE: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_EVPE: - check_insn(ctx, ASE_MT); + check_cp0_mt(ctx); gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); break; --=20 2.7.4